公开(公告)号：US11677003B2

公开(公告)日：2023-06-13

申请号：US17228090

申请日：2021-04-12

申请人： Sony Group Corporation

发明人： Seung Hoon Sung ,  Seiyon Kim ,  Kelin J. Kuhn ,  Willy Rachmady ,  Jack T. Kavalieros

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  B41F3/46 ,  B41F17/08 ,  B41N10/04 ,  H01L21/033 ,  H01L29/78

CPC分类号： H01L29/1033 ,  B41F3/46 ,  B41F17/08 ,  B41N10/04 ,  H01L21/0332 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  B41N2210/04 ,  B41N2210/14 ,  Y10T156/10

摘要： A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

公开(公告)号：US12046637B2

公开(公告)日：2024-07-23

申请号：US18318437

申请日：2023-05-16

申请人： Sony Group Corporation

发明人： Seung Hoon Sung ,  Seiyon Kim ,  Kelin J. Kuhn ,  Willy Rachmady ,  Jack T. Kavalieros

IPC分类号： H01L29/10 ,  B41F3/46 ,  B41F17/08 ,  B41N10/04 ,  H01L21/033 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/1033 ,  B41F3/46 ,  B41F17/08 ,  B41N10/04 ,  H01L21/0332 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  B41N2210/04 ,  B41N2210/14 ,  Y10T156/10

摘要： A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.