公开(公告)号：US06372594B1

公开(公告)日：2002-04-16

申请号：US09749785

申请日：2000-12-28

申请人： Soo Kun Jeon ,  Moon Jung Kim ,  Kyoung Hoon Yang ,  Young Se Kwon

发明人： Soo Kun Jeon ,  Moon Jung Kim ,  Kyoung Hoon Yang ,  Young Se Kwon

IPC分类号： H01L21331

摘要： Disclosed is a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process. The method involves the steps of laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively, defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner, selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist, and depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate. In accordance with the present invention, a reliable submicron gate can be fabricated using a simple anisotropic wet etch process and an inexpensive contact aligner. Accordingly, the manufacturing costs can be reduced. In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter, thereby achieving a reduction in base resistance, by virtue of a self-alignment using a V-shaped submicron gate.

公开(公告)号：US20060132168A1

公开(公告)日：2006-06-22

申请号：US11153138

申请日：2005-06-15

申请人： Kyoung Hoon Yang ,  Sun Choi

发明人： Kyoung Hoon Yang ,  Sun Choi

IPC分类号： H03K19/195

CPC分类号： B82Y10/00 ,  H03K3/315 ,  H03K19/10

摘要： The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits. The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling diode logic, and at the same time provide new MOBILE based logic functions. Wherein, the difficulty for input voltage adjustment is resolved by replacing the input part with a CML input driving gate, and speed problem due to transistor is resolved. Moreover, a plurality of logic functions such as inverted return-to-zero D flip-flop, non-inverted return-to-zero D flip-flop, return-to-zero OR gate, return-to-zero D flip-flop generating differential output, and optical flip-flop are implemented.

摘要翻译： 本发明涉及使用MOBILE（单稳态Nistable转换逻辑元件）配置的CML（电流模式逻辑）型输入驱动方法和隧道二极管逻辑，作为非常高速数字逻辑电路的种类。 本发明的目的是改进作为现有隧道二极管逻辑的MOBILE电路配置的缺点，同时提供新的基于MOBILE的逻辑功能。 其中，通过用CML输入驱动门代替输入部分来解决输入电压调整的难度，解决晶体管导致的速度问题。 此外，还有多个逻辑功能，例如反向归零D触发器，非反相返回到零D触发器，归零或或门，归零D触发器 产生差分输出和光学触发器。

公开(公告)号：US06780702B2

公开(公告)日：2004-08-24

申请号：US10271246

申请日：2002-10-15

申请人： Myoung Hoon Yoon ,  Kyoung Hoon Yang

发明人： Myoung Hoon Yoon ,  Kyoung Hoon Yang

IPC分类号： H01L218249

CPC分类号： H01L29/66318 ,  H01L21/30612 ,  H01L29/0657 ,  H01L29/7371

摘要： When InP DHBTs are located in parallel to a crystallographical direction of , there are several advantages in the aspect of device property such as reliability. But, in case of a direction parallel to a general , there exists the limitation in reducing base-collector parasitic capacitance only by collector over-etching technique due to poor lateral-etching characteristic of the InP collector. To overcome such a problem mentioned above and improve device performance, the present invention provides a method of reducing parasitic capacitance using underneath crystallographically selective wet etching, thereby providing a self-alignable, structurally stable device.

摘要翻译： 当InP DHBT平行于<011>的晶体学方向时，在诸如可靠性的器件特性方面存在若干优点。 但是，在平行于一般<011>的方向的情况下，由于InP集电极的横向蚀刻特性差，存在仅通过集电极过蚀刻技术来减小集电极的寄生电容的限制。为了克服这种问题 提高了器件性能，本发明提供了一种使用晶体选择性湿蚀刻下降寄生电容的方法，从而提供了可自对准的结构稳定的器件。

公开(公告)号：US07816972B2

公开(公告)日：2010-10-19

申请号：US11943074

申请日：2007-11-20

申请人： Kyoung Hoon Yang ,  Tae Ho Kim

发明人： Kyoung Hoon Yang ,  Tae Ho Kim

IPC分类号： H03K17/62

CPC分类号： H03K19/1738 ,  H04J3/047

摘要： Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1 and D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and R1). The second differential output unit receives NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generates differential RZ-mode outputs (R2 and R2). The selection unit receives the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

摘要翻译： 这里公开了一种多路复用器电路。 多路复用器电路包括第一差分输出单元，第二差分输出单元和选择单元。 第一差分输出单元接收NRZ输入信号（D1和D1）和时钟信号（CLK），并产生差分RZ模式输出（R1和R1）。 第二差分输出单元接收NRZ输入信号（D2和D2）和反相时钟信号（CLK），并产生差分RZ模式输出（R2和R2）。 选择单元接收在第一差分输出单元和第二差分输出单元处产生的RZ模式输出信号（R1，R1，R2和R2），并且在时钟信号（CLK）的每个半周期中产生NRZ模式输出， 。

公开(公告)号：US07573017B2

公开(公告)日：2009-08-11

申请号：US11859086

申请日：2007-09-21

申请人： Kyoung Hoon Yang ,  Ha Joon Lee

发明人： Kyoung Hoon Yang ,  Ha Joon Lee

IPC分类号： H01J40/14 ,  H01L27/00

CPC分类号： H01L27/14609 ,  H04N5/35518 ,  H04N5/3745

摘要： Disclosed herein is an active pixel sensor having a first transistor amplifying voltage generated in response to light at an integration node; a second transistor selects a specific pixel from a pixel array; a third transistor resets voltage of the integration node to voltage supplied from VDD during a reset period; a fourth transistor connects a photogate capacitance to the integration node increasing a dynamic range when the voltage of the integration node is VDD-Vth; a fifth transistor generates a signal voltage in a logarithmic response to light when the voltage of the integration node is logarithmic bias voltage-Vth; and a photodiode to convert photons into electron pairs in a depletion layer, causing signal charges to be accumulated when light is incident from outside.

摘要翻译： 这里公开了一种有源像素传感器，其具有响应于集成节点处的光而产生的第一晶体管放大电压; 第二晶体管从像素阵列中选择特定像素; 在复位期间，第三晶体管将积分节点的电压复位为从VDD提供的电压; 第四晶体管将光栅电容连接到积分节点，当积分节点的电压为VDD-Vth时增加动态范围; 当积分节点的电压为对数偏置电压Vth时，第五晶体管产生对光的对数响应的信号电压; 以及用于将光子转换成耗尽层中的电子对的光电二极管，当光从外部入射时，引起信号电荷的累积。

公开(公告)号：US07403032B2

公开(公告)日：2008-07-22

申请号：US11153138

申请日：2005-06-15

申请人： Kyoung Hoon Yang ,  Sun Kyu Choi

发明人： Kyoung Hoon Yang ,  Sun Kyu Choi

IPC分类号： H03K19/195

CPC分类号： B82Y10/00 ,  H03K3/315 ,  H03K19/10

摘要： The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits.The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling diode logic, and at the same time provide new MOBILE based logic functions. Wherein, the difficulty for input voltage adjustment is resolved by replacing the input part with a CML input driving gate, and speed problem due to transistor is resolved. Moreover, a plurality of logic functions such as inverted return-to-zero D flip-flop, non-inverted return-to-zero D flip-flop, return-to-zero OR gate, return-to-zero D flip-flop generating differential output, and optical flip-flop are implemented.

摘要翻译： 本发明涉及使用MOBILE（单稳态Nistable转换逻辑元件）配置的CML（电流模式逻辑）型输入驱动方法和隧道二极管逻辑，作为非常高速数字逻辑电路的种类。 本发明的目的是改进作为现有隧道二极管逻辑的MOBILE电路配置的缺点，同时提供新的基于MOBILE的逻辑功能。 其中，通过用CML输入驱动门代替输入部分来解决输入电压调整的难度，解决晶体管导致的速度问题。 此外，还有多个逻辑功能，例如反向归零D触发器，非反相返回到零D触发器，归零或或门，归零D触发器 产生差分输出和光学触发器。