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    METHOD FOR ESTIMATING PROCESSOR ENERGY USAGE
    1.
    发明申请
    METHOD FOR ESTIMATING PROCESSOR ENERGY USAGE 有权
    估算处理器能量使用的方法

    公开(公告)号：US20070136720A1

    公开(公告)日：2007-06-14

    申请号：US11609102

    申请日：2006-12-11

    Applicant: Sourav Roy ,  Ashish Mathur

    Inventor： Sourav Roy ,  Ashish Mathur

    IPC: G06F9/45

    CPC classification number: G06F9/30 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3891 ,  G06F11/3062

    Abstract: A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.

    Abstract translation: 一种用于估计由非常长的指令字（VLIW）处理器执行的程序代码的能量使用的方法。 程序代码包括多个指令，它们被组织为被称为执行集的组。 执行集的指令同时执行。 确定程序代码的每个执行集合的无操作（NOP）能量和增量指令能量以计算每个执行集的基本能量。 然后计算每个执行集合的执行间集合能量。 每个执行集合的估计能量使用通过将相应的执行中的集合能量相加到基本能量来确定。 然后计算由于执行程序代码而消耗的失速能量。 最后，通过将停顿能量加到所有执行集合的确定的能量来确定程序代码的估计能量使用。

    Method for estimating processor energy usage
    2.
    发明授权
    Method for estimating processor energy usage 有权
    估算处理器能耗的方法

    公开(公告)号：US07802241B2

    公开(公告)日：2010-09-21

    申请号：US11609102

    申请日：2006-12-11

    Applicant: Sourav Roy ,  Ashish Mathur

    Inventor： Sourav Roy ,  Ashish Mathur

    IPC: G06F9/45 ,  G06F9/46

    CPC classification number: G06F9/30 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3891 ,  G06F11/3062

    Abstract: A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.

    Abstract translation: 一种用于估计由非常长的指令字（VLIW）处理器执行的程序代码的能量使用的方法。 程序代码包括多个指令，它们被组织为被称为执行集的组。 执行集的指令同时执行。 确定程序代码的每个执行集合的无操作（NOP）能量和增量指令能量以计算每个执行集的基本能量。 然后计算每个执行集合的执行间集合能量。 每个执行集合的估计能量使用通过将相应的执行中的集合能量相加到基本能量来确定。 然后计算由于执行程序代码而消耗的失速能量。 最后，通过将停顿能量加到所有执行集合的确定的能量来确定程序代码的估计能量使用。

    Increasing precision in multi-stage processing of digital signals
    8.
    发明授权
    Increasing precision in multi-stage processing of digital signals 失效

    公开(公告)号：US06996597B2

    公开(公告)日：2006-02-07

    申请号：US10092927

    申请日：2002-03-06

    Applicant: Ashish Mathur ,  Srinivasan Gopalaswamy ,  Pradeep Jain

    Inventor： Ashish Mathur ,  Srinivasan Gopalaswamy ,  Pradeep Jain

    IPC: G06F7/38

    CPC classification number: H04L27/2628

    Abstract: Precision of multi-stage digital signal processing is increased by preserving least significant bits of one or more output samples of a particular processing stage, having finite word widths, while avoiding the loss of most significant bits. The technique is applicable to one or more stages of multi-stage digital signal processing, thereby increasing precision therein and the signal-to-noise ratio. A plurality of output samples are calculated using a plurality of input samples, and the dynamic range of one or more of the output samples is decreased if the output sample can be represented in a smaller dynamic range without losing a significant bit. The input samples of a particular stage, obtained from the output samples of a previous stage, may further be normalized so that the input samples are represented in the same dynamic range before being processed.

    Multi-threaded system for performing atomic binary translations
    9.
    发明授权
    Multi-threaded system for performing atomic binary translations 有权
    用于执行原子二进制翻译的多线程系统

    公开(公告)号：US09053035B1

    公开(公告)日：2015-06-09

    申请号：US14088446

    申请日：2013-11-25

    Applicant: Ashish Mathur ,  Sandeep Jain

    Inventor： Ashish Mathur ,  Sandeep Jain

    IPC: G06F12/02 ,  G06F12/08

    CPC classification number: G06F9/3004 ,  G06F8/45 ,  G06F8/52 ,  G06F9/45558

    Abstract: A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

    Abstract translation: 多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。 存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。 条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本 链接指令与存储在存储条件共享存储器地址中的数据相同。

    MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS
    10.
    发明申请
    MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS 有权
    用于执行原子二进制翻译的多线程系统

    公开(公告)号：US20150149725A1

    公开(公告)日：2015-05-28

    申请号：US14088446

    申请日：2013-11-25

    Applicant: Ashish Mathur ,  Sandeep Jain

    Inventor： Ashish Mathur ,  Sandeep Jain

    IPC: G06F12/08

    CPC classification number: G06F9/3004 ,  G06F8/45 ,  G06F8/52 ,  G06F9/45558

    Abstract: A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

    Abstract translation: 多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。 存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。 条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本 链接指令与存储在存储条件共享存储器地址中的数据相同。

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