公开(公告)号：US20090045472A1

公开(公告)日：2009-02-19

申请号：US11837709

申请日：2007-08-13

申请人： Srinivasan Chakravarthi ,  Narendra Singh Mehta ,  Rajesh Khamankar ,  Ajith Varghese ,  Malcolm J. Bevan ,  Tad Grider

发明人： Srinivasan Chakravarthi ,  Narendra Singh Mehta ,  Rajesh Khamankar ,  Ajith Varghese ,  Malcolm J. Bevan ,  Tad Grider

IPC分类号： H01L29/94 ,  H01L21/8234

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L21/28035 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm−3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.

摘要翻译： 半导体器件包括形成在衬底中并具有至少约5E18cm-3的氮浓度的源极/漏极区域。 栅极电介质位于衬底上并且在源/漏区之间。 栅极侧壁间隔物位于所述源极/漏极区域之上。 包括多晶硅的氮掺杂电极位于栅极电介质上方。 电极的氮浓度大于源极/漏极区域中的氮浓度。

公开(公告)号：US07572693B2

公开(公告)日：2009-08-11

申请号：US11462541

申请日：2006-08-04

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. McKee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. McKee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/04

CPC分类号： H01L21/28035 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.

摘要翻译： 公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。 图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。 此后，将掺杂剂选择性地植入到暴露的栅极结构中。

公开(公告)号：US20060270139A1

公开(公告)日：2006-11-30

申请号：US11462528

申请日：2006-08-04

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin McKee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin McKee

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/28035 ,  H01L21/324 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

摘要翻译： 公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。 图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。 此后，将掺杂剂选择性地注入到暴露的栅极结构中。

公开(公告)号：US07098098B2

公开(公告)日：2006-08-29

申请号：US10226536

申请日：2002-08-23

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. Mckee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. Mckee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/04

CPC分类号： H01L29/66545 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/324 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

公开(公告)号：US20060270140A1

公开(公告)日：2006-11-30

申请号：US11462541

申请日：2006-08-04

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin McKee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin McKee

IPC分类号： H01L21/8238

CPC分类号： H01L21/28035 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.

摘要翻译： 公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。 图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。 此后，将掺杂剂选择性地植入到暴露的栅极结构中。

公开(公告)号：US06682994B2

公开(公告)日：2004-01-27

申请号：US10123686

申请日：2002-04-16

申请人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. Mckee

发明人： F. Scott Johnson ,  Tad Grider ,  Benjamin P. Mckee

IPC分类号： H01L213205

CPC分类号： H01L21/28035 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/4916 ,  H01L29/6659

摘要： Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.

摘要翻译： 公开了将要形成MOS晶体管栅极的半导体器件制造的方法。 形成多晶硅栅极结构和侧壁间隔物，露出栅极侧壁的上部。 使用角度注入处理以将掺杂剂赋予栅极结构的顶部和暴露的侧壁部分以减轻多余的损耗。