公开(公告)号：US08829570B2

公开(公告)日：2014-09-09

申请号：US13416152

申请日：2012-03-09

申请人： Srivatsan Parthasarathy ,  Javier A. Salcedo ,  Shuyun Zhang

发明人： Srivatsan Parthasarathy ,  Javier A. Salcedo ,  Shuyun Zhang

IPC分类号： H01L33/00

CPC分类号： H01L27/0262

摘要： A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 μA at 20V DC.

摘要翻译： 公开了一种用于异质结集成电路的开关装置。 根据一个方面，开关装置被配置为保护电路免受静电放电（ESD）事件的影响。 开关器件包括被配置为电浮置的第二基极接触区域，耦合到开关器件的第一输入端子的第一基极接触区域和集电极接触区域以及耦合到开关器件的发射极接触区域 第二输入端子。 部分地由于第一基极接触区域和第二基极接触区域之间的电容耦合，开关器件表现出低瞬态触发电压和对ESD事件的快速响应。 此外，开关器件表现出高直流触发电压（例如，大于20V），同时在操作期间保持较低的漏电流（例如，在20V DC时小于约0.5μA）。

公开(公告)号：US20130234209A1

公开(公告)日：2013-09-12

申请号：US13416152

申请日：2012-03-09

申请人： Srivatsan Parthasarathy ,  Javier A. Salcedo ,  Shuyun Zhang

发明人： Srivatsan Parthasarathy ,  Javier A. Salcedo ,  Shuyun Zhang

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L27/0262

摘要： A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 μA at 20V DC.

摘要翻译： 公开了一种用于异质结集成电路的开关装置。 根据一个方面，开关装置被配置为保护电路免受静电放电（ESD）事件的影响。 开关器件包括被配置为电浮置的第二基极接触区域，耦合到开关器件的第一输入端子的第一基极接触区域和集电极接触区域以及耦合到开关器件的发射极接触区域 第二输入端子。 部分地由于第一基极接触区域和第二基极接触区域之间的电容耦合，开关器件表现出低瞬态触发电压和对ESD事件的快速响应。 此外，开关器件表现出高直流触发电压（例如，大于20V），同时在操作期间保持相对较低的漏电流（例如，在20V DC时小于约0.5μA）。

公开(公告)号：US07839233B2

公开(公告)日：2010-11-23

申请号：US12009919

申请日：2008-01-23

申请人： Yibing Zhao ,  Shuyun Zhang

发明人： Yibing Zhao ,  Shuyun Zhang

IPC分类号： H01P1/22 ,  H03H7/24

CPC分类号： H01P1/22

摘要： A π-type voltage-controlled variable attenuator is disclosed. The variable attenuator may include variably resistive components in the series and shunt arms. The variably resistive components may be implemented as field effect transistors. The shunt arms may be coupled to the series arm, and the variable attenuator may lack capacitors between the series arm and shunt arms. The series arm and shunt arms may display variable resistances which, in combination, operate to provide a variable level of attenuation of an input signal. The variable attenuator may provide any level of attenuation of an input signal over a wide frequency range. The variable attenuator may be implemented as an integrated circuit.

摘要翻译： 公开了一种压控型可变衰减器。 可变衰减器可以包括串联和分流臂中的可变电阻分量。 可变电阻分量可以被实现为场效应晶体管。 分流臂可以耦合到串联臂，并且可变衰减器可以在串联臂和分流臂之间缺少电容器。 串联臂和分流臂可以显示可变电阻，其组合地操作以提供输入信号的可变衰减水平。 可变衰减器可以在宽的频率范围内提供输入信号的任何衰减水平。 可变衰减器可以被实现为集成电路。

公开(公告)号：US07508249B2

公开(公告)日：2009-03-24

申请号：US11491717

申请日：2006-07-24

申请人： Shuyun Zhang ,  Yibing Zhao

发明人： Shuyun Zhang ,  Yibing Zhao

IPC分类号： H03K17/687

CPC分类号： H03F3/193 ,  H03F1/301 ,  H03F1/3205 ,  H03F3/195 ,  H03F3/345 ,  H03F2200/63

摘要： A transistor cell includes a first stage comprising a first transistor that is coupled to a RC filter arrangement. A second stage has a second transistor that is coupled to the first stage. The linearity of the transistor cell is improved by shifting the DC bias point so that the first stage is biased at a high quiescent current while the second stage is biased at a low quiescent current.

摘要翻译： 晶体管单元包括第一级，其包括耦合到RC滤波器装置的第一晶体管。 第二级具有耦合到第一级的第二晶体管。 通过移动DC偏置点来改善晶体管单元的线性，使得第一级被偏置在高静态电流，而第二级被偏置在低静态电流。

公开(公告)号：US20070024352A1

公开(公告)日：2007-02-01

申请号：US11491717

申请日：2006-07-24

申请人： Shuyun Zhang ,  Yibing Zhao

发明人： Shuyun Zhang ,  Yibing Zhao

IPC分类号： H03K17/687 ,  G05F1/10 ,  H03B1/00

CPC分类号： H03F3/193 ,  H03F1/301 ,  H03F1/3205 ,  H03F3/195 ,  H03F3/345 ,  H03F2200/63

摘要： A transistor cell includes a first stage comprising a first transistor that is coupled to a RC filter arrangement. A second stage has a second transistor that is coupled to the first stage. The linearity of the transistor cell is improved by shifting the DC bias point so that the first stage is biased at a high quiescent current while the second stage is biased at a low quiescent current.

摘要翻译： 晶体管单元包括第一级，其包括耦合到RC滤波器装置的第一晶体管。 第二级具有耦合到第一级的第二晶体管。 通过移动DC偏置点来改善晶体管单元的线性，使得第一级被偏置在高静态电流，而第二级被偏置在低静态电流。

公开(公告)号：US07750734B2

公开(公告)日：2010-07-06

申请号：US12077895

申请日：2008-03-21

申请人： Pavel Bretchko ,  Shuyun Zhang ,  Royal Gosser

发明人： Pavel Bretchko ,  Shuyun Zhang ,  Royal Gosser

IPC分类号： H03F1/26

CPC分类号： H03F1/32 ,  H03F1/22 ,  H03F1/223 ,  H03F1/3205 ,  H03F1/3223 ,  H03F1/34 ,  H03F2200/135 ,  H03F2200/93

摘要： Circuits and methods for reducing distortion in an amplified signal are disclosed. The circuits and methods may use multiple single-ended gain stages to produce multiple amplified signals. The amplified signals may be processed in combination to produce a resulting output signal having little, or no, distortion. The circuits may be implemented on a single chip as integrated circuits.

摘要翻译： 公开了用于减小放大信号中的失真的电路和方法。 电路和方法可以使用多个单端增益级来产生多个放大信号。 放大的信号可以组合处理以产生具有很少或没有失真的结果输出信号。 电路可以作为集成电路在单个芯片上实现。

公开(公告)号：US20090184785A1

公开(公告)日：2009-07-23

申请号：US12009919

申请日：2008-01-23

申请人： Yibing Zhao ,  Shuyun Zhang

发明人： Yibing Zhao ,  Shuyun Zhang

IPC分类号： H01P1/22

CPC分类号： H01P1/22

摘要： A π-type voltage-controlled variable attenuator is disclosed. The variable attenuator may include variably resistive components in the series and shunt arms. The variably resistive components may be implemented as field effect transistors. The shunt arms may be coupled to the series arm, and the variable attenuator may lack capacitors between the series arm and shunt arms. The series arm and shunt arms may display variable resistances which, in combination, operate to provide a variable level of attenuation of an input signal. The variable attenuator may provide any level of attenuation of an input signal over a wide frequency range. The variable attenuator may be implemented as an integrated circuit.

摘要翻译： 公开了一种pi型压控可变衰减器。 可变衰减器可以包括串联和分流臂中的可变电阻分量。 可变电阻分量可以被实现为场效应晶体管。 分流臂可以耦合到串联臂，并且可变衰减器可以在串联臂和分流臂之间缺少电容器。 串联臂和分流臂可以显示可变电阻，其组合地操作以提供输入信号的可变衰减水平。 可变衰减器可以在宽的频率范围内提供输入信号的任何衰减水平。 可变衰减器可以被实现为集成电路。

公开(公告)号：US07098755B2

公开(公告)日：2006-08-29

申请号：US10620395

申请日：2003-07-16

申请人： Yibing Zhao ,  Shuyun Zhang ,  Robert J. McMorrow

发明人： Yibing Zhao ,  Shuyun Zhang ,  Robert J. McMorrow

IPC分类号： H01P1/10

CPC分类号： H03K17/6871 ,  H03K17/102 ,  H03K17/693

摘要： A high performance single-pole-double-throw (SPDT) Transmitter/Receiver (T/R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an antenna port, a transmitter branch coupled to a transmitter port through a plurality of multi-gate FETs in series and a receiver branch coupled to a receiver port through a plurality of multi-gate FETs in series. When a high power signal passes from the transmitter port to the antenna port through the transmitter branch, the receiver branch is required to be shut off electrically to prevent the high power signal from leaking to receiver port. This leakage can degrade the isolation of the switch and cause harmonic distortion. Furthermore, the transmitter branch is required to provide a resistance as small as possible to reduce the power loss when it passes through the transmitter branch to the antenna port. In the receiver branch, two of the gate metals in the multi-gate FETs are fabricated with gate sizes several times larger than the others. Furthermore, a heavily doped cap layer is utilized between the gate fingers in a multi-gate FET to reduce the channel resistance of FET, thereby lowering the insertion loss.

摘要翻译： 高性能单刀双掷（SPDT）发射器/接收器（T / R）FET开关利用多个串联多栅极FET实现低插入损耗，低谐波失真和高功率处理能力。 SPDT开关包括天线端口，通过串联的多个多栅极FET耦合到发射器端口的发射器分支和通过串联的多个多栅极FET耦合到接收器端口的接收器支路。 当高功率信号通过发射机分支从发射机端口传送到天线端口时，接收器分支需要电气关闭，以防止高功率信号泄漏到接收机端口。 这种泄漏可能会降低开关的隔离并导致谐波失真。 此外，发射机支路需要提供尽可能小的电阻，以便当其通过发射机分支到天线端口时降低功率损耗。 在接收器支路中，多栅极FET中的栅极金属中的两个被栅极尺寸制造成比其他栅极大几倍。 此外，在多栅极FET中的栅极指之间利用重掺杂的覆盖层来降低FET的沟道电阻，从而降低插入损耗。

公开(公告)号：US07755415B2

公开(公告)日：2010-07-13

申请号：US11409622

申请日：2006-04-24

申请人： Shuyun Zhang

发明人： Shuyun Zhang

IPC分类号： H03K17/687

CPC分类号： H03D7/125

摘要： A transistor cell is provided that includes transistors arranged to turn on for different voltages applied to a control terminal of the transistor cell. The transistor cell can include a first transistor having a gate, a source, and a drain, and a second transistor having a gate, a source, and a drain, wherein the source of the second transistor is coupled to the source of the first transistor, and the drain of the second transistor is coupled to the drain of the first transistor. The transistor cell can further include a first resistor coupled between the gate of the first transistor and the gate of the second transistor. A frequency mixer is also provided that includes at least one transistor cell.

摘要翻译： 提供晶体管单元，其包括晶体管，其被布置为对施加到晶体管单元的控制端子的不同电压导通。 晶体管单元可以包括具有栅极，源极和漏极的第一晶体管和具有栅极，源极和漏极的第二晶体管，其中第二晶体管的源极耦合到第一晶体管的源极 并且第二晶体管的漏极耦合到第一晶体管的漏极。 晶体管单元还可以包括耦合在第一晶体管的栅极和第二晶体管的栅极之间的第一电阻器。 还提供了包括至少一个晶体管单元的混频器。

公开(公告)号：US20080231370A1

公开(公告)日：2008-09-25

申请号：US12077895

申请日：2008-03-21

申请人： Pavel Bretchko ,  Shuyun Zhang ,  Royal Gosser

发明人： Pavel Bretchko ,  Shuyun Zhang ,  Royal Gosser

IPC分类号： H03F1/26 ,  H03G3/20

CPC分类号： H03F1/32 ,  H03F1/22 ,  H03F1/223 ,  H03F1/3205 ,  H03F1/3223 ,  H03F1/34 ,  H03F2200/135 ,  H03F2200/93

摘要： Circuits and methods for reducing distortion in an amplified signal are disclosed. The circuits and methods may use multiple single-ended gain stages to produce multiple amplified signals. The amplified signals may be processed in combination to produce a resulting output signal having little, or no, distortion. The circuits may be implemented on a single chip as integrated circuits.

摘要翻译： 公开了用于减小放大信号中的失真的电路和方法。 电路和方法可以使用多个单端增益级来产生多个放大信号。 放大的信号可以组合处理以产生具有很少或没有失真的结果输出信号。 电路可以作为集成电路在单个芯片上实现。