公开(公告)号：US08829570B2

公开(公告)日：2014-09-09

申请号：US13416152

申请日：2012-03-09

申请人： Srivatsan Parthasarathy ,  Javier A. Salcedo ,  Shuyun Zhang

发明人： Srivatsan Parthasarathy ,  Javier A. Salcedo ,  Shuyun Zhang

IPC分类号： H01L33/00

CPC分类号： H01L27/0262

摘要： A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 μA at 20V DC.

摘要翻译： 公开了一种用于异质结集成电路的开关装置。 根据一个方面，开关装置被配置为保护电路免受静电放电（ESD）事件的影响。 开关器件包括被配置为电浮置的第二基极接触区域，耦合到开关器件的第一输入端子的第一基极接触区域和集电极接触区域以及耦合到开关器件的发射极接触区域 第二输入端子。 部分地由于第一基极接触区域和第二基极接触区域之间的电容耦合，开关器件表现出低瞬态触发电压和对ESD事件的快速响应。 此外，开关器件表现出高直流触发电压（例如，大于20V），同时在操作期间保持较低的漏电流（例如，在20V DC时小于约0.5μA）。

公开(公告)号：US08610251B1

公开(公告)日：2013-12-17

申请号：US13486885

申请日：2012-06-01

申请人： Javier A Salcedo

发明人： Javier A Salcedo

IPC分类号： H01L27/02

CPC分类号： H01L29/747 ,  H01L27/0259 ,  H01L27/0921

摘要： A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling.

摘要翻译： 双向保护装置包括双极NPN双极晶体管，其包括由第一n阱区域形成的发射极/集电极，由p阱区域形成的基极和由第二n阱形成的集电极/发射极 地区。 在第一和第二n阱区域中形成P型有源区，以形成PNPNP结构，该PNPNP结构使用由n型槽和p型槽构成的双槽隔离与基板隔离。 双槽隔离通过防止与PNPNP结构相关联的阱将载流子注入到衬底中来防止在集成电路供电的应力条件期间引起的闩锁。 选择与PNPNP结构相关联的有源区和阱的尺寸，间距和掺杂浓度以提供对触发和保持电压特性的微调控制，以使双向保护装置能够在使用低电压的高电压应用中实现 电压精密接口信号。

公开(公告)号：US20130320498A1

公开(公告)日：2013-12-05

申请号：US13486885

申请日：2012-06-01

申请人： Javier A. Salcedo

发明人： Javier A. Salcedo

IPC分类号： H01L29/73

CPC分类号： H01L29/747 ,  H01L27/0259 ,  H01L27/0921

摘要： A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling.

摘要翻译： 双向保护装置包括双极NPN双极晶体管，其包括由第一n阱区域形成的发射极/集电极，由p阱区域形成的基极和由第二n阱形成的集电极/发射极 地区。 在第一和第二n阱区域中形成P型有源区，以形成PNPNP结构，该PNPNP结构使用由n型槽和p型槽构成的双槽隔离与基板隔离。 双槽隔离通过防止与PNPNP结构相关联的阱将载流子注入到衬底中来防止在集成电路供电的应力条件期间引起的闩锁。 选择与PNPNP结构相关联的有源区和阱的尺寸，间距和掺杂浓度以提供对触发和保持电压特性的微调控制，以使双向保护装置能够在使用低电压的高电压应用中实现 电压精密接口信号。

公开(公告)号：US08432651B2

公开(公告)日：2013-04-30

申请号：US12797463

申请日：2010-06-09

申请人： Javier A Salcedo ,  David Casey ,  Graham McCorkell

发明人： Javier A Salcedo ,  David Casey ,  Graham McCorkell

IPC分类号： H02H9/04 ,  H02H3/22

CPC分类号： H01L27/06 ,  H01L23/60 ,  H01L27/0251 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

摘要： Apparatuses and methods for protecting electronic circuits are disclosed. In one embodiment, an apparatus for providing protection from transient signals comprises an integrated circuit, a pad on a surface of the integrated circuit, and a configurable protection circuit within the integrated circuit. The configurable protection circuit is electrically connected to the pad. The configurable protection circuit comprises a plurality of subcircuits arranged in a cascade, and selection of one or more of the plurality of the subcircuits for operation determines at least one of a holding voltage or a trigger voltage of the configurable protection circuit.

摘要翻译： 公开了用于保护电子电路的装置和方法。 在一个实施例中，用于从瞬态信号提供保护的装置包括集成电路，集成电路的表面上的焊盘以及集成电路内的可配置保护电路。 可配置的保护电路电连接到焊盘。 可配置保护电路包括以级联布置的多个子电路，并且用于操作的多个子电路中的一个或多个的选择确定可配置保护电路的保持电压或触发电压中的至少一个。

公开(公告)号：US08422187B2

公开(公告)日：2013-04-16

申请号：US12830098

申请日：2010-07-02

申请人： Srivatsan Parthasarathy ,  Javier A Salcedo

发明人： Srivatsan Parthasarathy ,  Javier A Salcedo

IPC分类号： H02H3/22

CPC分类号： H02H3/22 ,  H01L27/0259 ,  H02H9/046

摘要： Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.

摘要翻译： 公开了用于提供瞬时电气事件保护的装置和方法。 在一个实施例中，一种装置包括检测和定时电路，电流放大电路和钳位电路。 检测和定时电路被配置为检测在第一节点处的瞬时电事件的存在或不存在，并且在检测到瞬态电事件时产生第一持续时间的第一电流。 电流放大电路被配置为从检测和定时电路接收第一电流并且放大第一电流以产生第二电流。 钳位电路电连接在第一节点和第二节点之间，并接收用于激活的第二电流。 钳位电路被配置为响应于第二电流来激活第一和第二节点之间的低阻抗路径，并且否则去激活低阻抗路径。

公开(公告)号：US20130032882A1

公开(公告)日：2013-02-07

申请号：US13198208

申请日：2011-08-04

申请人： Javier A. Salcedo ,  Michael Lynch ,  Brian Moane

发明人： Javier A. Salcedo ,  Michael Lynch ,  Brian Moane

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L27/0262 ,  H01L27/0921

摘要： Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

摘要翻译： 公开了双向阻断电压保护装置及其形成方法。 在一个实施例中，保护装置包括n阱以及设置在n阱的相对侧上的第一和第二p阱。 第一p阱包括第一P +区和第一N +区，第二p阱包括第二P +区和第二N +区。 该装置还包括沿着n阱和第一p阱的边界设置的第三P +区和沿着n阱和第二p阱的边界设置的第四P +区。 第一栅极设置在第一N +区域和第三P +区域之间，第二栅极设置在第二N +区域和第四P +区域之间。 该器件在高能量应力事件期间提供双向阻断电压保护，包括在非常低至中等摆幅电压下工作的应用。

公开(公告)号：US20120306013A1

公开(公告)日：2012-12-06

申请号：US13152867

申请日：2011-06-03

申请人： Colm Donovan ,  Javier A. Salcedo

发明人： Colm Donovan ,  Javier A. Salcedo

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0285

摘要： Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected to the pad, a first supply voltage, and a drain of the PMOS transistor, respectively. The second NMOS transistor includes a gate, a drain, and a source electrically connected to a bias node, a second supply voltage, and a source of the PMOS transistor, respectively. The source of the second NMOS transistor is further electrically connected to a body of the PMOS transistor so as to prevent a current flowing from the drain of the PMOS transistor to the second supply voltage through the body of PMOS transistor when a transient signal event is received on the pad.

摘要翻译： 公开了金属氧化物半导体（MOS）保护电路及其形成方法。 在一个实施例中，集成电路包括焊盘，p型MOS（PMOS）晶体管以及第一和第二n型MOS（NMOS）晶体管。 第一NMOS晶体管分别包括漏极，源极和电连接到焊盘的栅极，PMOS晶体管的第一电源电压和漏极。 第二NMOS晶体管分别包括电连接到偏置节点，第二电源电压和PMOS晶体管的源极的栅极，漏极和源极。 第二NMOS晶体管的源极进一步电连接到PMOS晶体管的主体，以便当接收到瞬态信号事件时，防止电流从PMOS晶体管的漏极流过PMOS晶体管的主体 在垫上。

公开(公告)号：US08946822B2

公开(公告)日：2015-02-03

申请号：US13423720

申请日：2012-03-19

申请人： Javier A. Salcedo ,  Srivatsan Parthasarathy

发明人： Javier A. Salcedo ,  Srivatsan Parthasarathy

IPC分类号： H01L23/62

CPC分类号： H01L27/0262 ,  H01L21/8222 ,  H01L27/0259

摘要： Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

摘要翻译： 提供了精密混合信号电子电路保护的装置和方法。 在一个实施例中，一种装置包括p阱，n阱，多有源二极管结构，p型有源区和n型有源区。 多极二极管结构形成在n阱上，p型有源区形成在多功能二极管结构的第一侧上的n阱中，并且n型有源区沿着 在多活性二极管结构的第二侧上的p阱和n阱的边界。 在瞬态电气事件期间，该装置被配置为提供穿过多功能二极管结构之间和之下的导电路径，以便于在n型有源区域中注入载流子。 保护装置还可以包括在p阱上形成的另一个多有源二极管结构，以进一步增强对n型有源区的载流子注入。

公开(公告)号：US20130208385A1

公开(公告)日：2013-08-15

申请号：US13372327

申请日：2012-02-13

申请人： Javier A. Salcedo ,  David J. Clarke ,  Gavin P. Cosgrave ,  Yuhong Huang

发明人： Javier A. Salcedo ,  David J. Clarke ,  Gavin P. Cosgrave ,  Yuhong Huang

IPC分类号： H02H3/22

CPC分类号： H01L23/60 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： Harsh electrical environments integrated circuit protection for system-level robustness and methods of forming the same are provided. In one embodiment, a protection system includes dual-polarity high blocking voltage primary and secondary protection devices each electrically connected to a pad. The primary protection device has a current handling capability greater than a current handling capability of the secondary protection devices, and the secondary protection device has a turn-on speed that is faster than a turn-on speed of the primary protection device so as to decrease pad voltage overshoot when a fast transient electrical event occurs on the pad. Additionally, the holding voltage of the primary protection device is less than a holding voltage of the secondary protection device such that once the primary protection device has been activated the primary protection device clamps the pad voltage so as to minimize a flow of high current through the secondary protection device.

摘要翻译： 提供恶劣的电气环境集成电路保护系统级的鲁棒性及其形成方法。 在一个实施例中，保护系统包括每个电连接到焊盘的双极性高阻断电压初级和次级保护装置。 主保护装置具有大于二次保护装置的当前处理能力的电流处理能力，并且次级保护装置具有比主保护装置的接通速度快的开启速度，从而降低 当焊盘发生快速瞬态电事件时，焊盘电压过冲。 此外，主保护装置的保持电压小于二次保护装置的保持电压，使得一旦主保护装置被激活，主保护装置夹紧焊盘电压，以便最小化高电流流过 二次保护装置。

公开(公告)号：US08283695B2

公开(公告)日：2012-10-09

申请号：US13114895

申请日：2011-05-24

申请人： Javier A. Salcedo ,  Juin J. Liou ,  Joseph C. Bernier ,  Donald K. Whitney

发明人： Javier A. Salcedo ,  Juin J. Liou ,  Joseph C. Bernier ,  Donald K. Whitney

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L27/10 ,  H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.

摘要翻译： 通过定制实现，先进的亚微米硅化CMOS（互补金属氧化物半导体）/ BiCMOS（双极CMOS）技术获得具有10 V至40 V以上触发电压和相对较高保持电流的对称/非对称双向S形IV特性 具有嵌入镇流电阻58,58A，56,56A和外围保护环隔离88-86的P1-N2-P2-N1 // N1-P3-N3-P1侧向结构。 双向保护装置为高级CMOS / BiCMOS工艺提供高水平的静电放电（ESD）抗扰性，无闩锁问题。 ESD保护单元的新型设计适配多功能354 /互指向336布局方案允许放大保护结构的ESD性能和定制集成，而IV特性480可调整到集成电路（IC）的工作条件， 。 ESD保护电池使用TLP（传输线脉冲）技术和ESD标准测试，包括HBM（人体模型），MM（机器模型）和IEC（国际电工委员会）IEC 1000-4-2 ESD抗扰度标准 。 ESD保护性能也在高温（140°C）下得到证明。 单位面积双极性ESD保护水平的独特高比例，可实现半导体行业针对低成本和高密度导向IC设计优化的快速响应和紧凑型保护单元的集成。 针对超低于15 kV HBM，2 kV MM和16.5 kV IEC的亚微米技术，可以证明对称/非对称双极性ESD保护性能。