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公开(公告)号：US20110084726A1
公开(公告)日：2011-04-14
申请号：US12969424
申请日：2010-12-15
申请人： Stephan Habel , Stefan G. Block
发明人： Stephan Habel , Stefan G. Block
IPC分类号： H03K19/173
CPC分类号： H03K5/135 , G01R31/31858 , H03K3/011
摘要： A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
摘要翻译： 提供了一种方法和装置，用于将值存储在电路的处理寄存器中，该值指示制造电路的处理的强度，并且调整施加到由所述电路的同步存储元件接收的数据信号的输入延迟 电路基于存储值。
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公开(公告)号：US08078926B2
公开(公告)日：2011-12-13
申请号：US12558611
申请日：2009-09-14
IPC分类号： G01R31/28
CPC分类号： G01R31/31701 , G01R31/318541
摘要： An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.
摘要翻译： 对具有用于仅在测试使能线处于逻辑高值时才能进行集成电路的电气测试的测试使能线的类型的集成电路的改进以及仅在集成电路的电测试期间使用的输出线 电路，其中改进是当测试使能线处于逻辑低值时禁止输出线路中的状态改变的开关电路。 以这种方式，输出线在集成电路的功能使用期间不切换，并且不能成为在集成电路的功能使用期间由数据线承载的数据信号的侵略者。 此外，这些非开关输出线可以用作在数据线之间运行的保护迹线，进一步将数据线彼此电隔离。 此外，由于在集成电路的功能使用期间不切换，集成电路的总体功耗降低。
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公开(公告)号：US07944237B2
公开(公告)日：2011-05-17
申请号：US12969424
申请日：2010-12-15
申请人： Stephan Habel , Stefan G. Block
发明人： Stephan Habel , Stefan G. Block
IPC分类号： H03K19/173 , H03K19/00
CPC分类号： H03K5/135 , G01R31/31858 , H03K3/011
摘要： A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
摘要翻译： 提供了一种方法和装置，用于将值存储在电路的处理寄存器中，该值指示制造电路的处理的强度，并且调整施加到由所述电路的同步存储元件接收的数据信号的输入延迟 电路基于存储值。
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4.发明授权公开(公告)号：US07514974B2
公开(公告)日：2009-04-07
申请号：US11736931
申请日：2007-04-18
申请人： Stefan G. Block , Stephan Habel
发明人： Stefan G. Block , Stephan Habel
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0805
摘要： An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency.
摘要翻译： 提供了一种装置和方法，用于为集成电路芯片提供在芯片外部产生的电源电压供电。 在集成电路芯片上制造的环形振荡器产生片上时钟信号。 电源电压根据片内时钟信号的频率和参考时钟频率之间的差异而改变。
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公开(公告)号：US20110066905A1
公开(公告)日：2011-03-17
申请号：US12558611
申请日：2009-09-14
IPC分类号： G06F11/00
CPC分类号： G01R31/31701 , G01R31/318541
摘要： An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.
摘要翻译： 对具有用于仅在测试使能线处于逻辑高值时才能进行集成电路的电气测试的测试使能线的类型的集成电路的改进以及仅在集成电路的电测试期间使用的输出线 电路，其中改进是当测试使能线处于逻辑低值时禁止输出线路中的状态改变的开关电路。 以这种方式，输出线在集成电路的功能使用期间不切换，并且不能成为在集成电路的功能使用期间由数据线承载的数据信号的侵略者。 此外，这些非开关输出线可以用作在数据线之间运行的保护迹线，进一步将数据线彼此电隔离。 此外，由于在集成电路的功能使用期间不切换，集成电路的总体功耗降低。
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公开(公告)号：US07880498B2
公开(公告)日：2011-02-01
申请号：US11944488
申请日：2007-11-23
申请人： Stephan Habel , Stefan G. Block
发明人： Stephan Habel , Stefan G. Block
IPC分类号： H03K19/173
CPC分类号： H03K5/135 , G01R31/31858 , H03K3/011
摘要： A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
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公开(公告)号：US07650548B2
公开(公告)日：2010-01-19
申请号：US11696420
申请日：2007-04-04
申请人： Stefan G. Block , Stephan Habel
发明人： Stefan G. Block , Stephan Habel
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575
摘要： A scannable flip-flop and method are provided. The flip-flop includes a clock input, a normal data input, a test data input, a normal data output and a scan data output. The flip-flop has a normal operating mode during which the normal data output is enabled and the scan data output disabled and has a scan-shift mode during which the normal data output is disabled and the scan data output is enabled.
摘要翻译： 提供可扫描的触发器和方法。 触发器包括时钟输入，正常数据输入，测试数据输入，正常数据输出和扫描数据输出。 触发器具有正常工作模式，在该模式期间正常数据输出被使能，并且扫描数据输出被禁止并且具有扫描移位模式，在该模式期间禁止正常数据输出并且使能扫描数据输出。
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公开(公告)号：US20090134912A1
公开(公告)日：2009-05-28
申请号：US11944488
申请日：2007-11-23
申请人： Stephan Habel , Stefan G. Block
发明人： Stephan Habel , Stefan G. Block
IPC分类号： H03K19/00
CPC分类号： H03K5/135 , G01R31/31858 , H03K3/011
摘要： A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
摘要翻译： 提供了一种方法和装置，用于将值存储在电路的处理寄存器中，该值指示制造电路的处理的强度，并且调整施加到由所述电路的同步存储元件接收的数据信号的输入延迟 电路基于存储值。
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9.发明申请公开(公告)号：US20080258700A1
公开(公告)日：2008-10-23
申请号：US11736931
申请日：2007-04-18
申请人： Stefan G. Block , Stephan Habel
发明人： Stefan G. Block , Stephan Habel
IPC分类号： H02J1/00
CPC分类号： H03L7/0995 , H03L7/0805
摘要： An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency.
摘要翻译： 提供了一种装置和方法，用于为集成电路芯片提供在芯片外部产生的电源电压供电。 在集成电路芯片上制造的环形振荡器产生片上时钟信号。 电源电压根据片内时钟信号的频率和参考时钟频率之间的差异而改变。
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公开(公告)号：US20080250283A1
公开(公告)日：2008-10-09
申请号：US11696420
申请日：2007-04-04
申请人： Stefan G. Block , Stephan Habel
发明人： Stefan G. Block , Stephan Habel
IPC分类号： G06F3/00
CPC分类号： G01R31/318541 , G01R31/318575
摘要： A scannable flip-flop and method are provided. The flip-flop includes a clock input, a normal data input, a test data input, a normal data output and a scan data output. The flip-flop has a normal operating mode during which the normal data output is enabled and the scan data output disabled and has a scan-shift mode during which the normal data output is disabled and the scan data output is enabled.
摘要翻译： 提供可扫描的触发器和方法。 触发器包括时钟输入，正常数据输入，测试数据输入，正常数据输出和扫描数据输出。 触发器具有正常工作模式，在该模式期间正常数据输出被使能，并且扫描数据输出被禁止并且具有扫描移位模式，在该模式期间禁止正常数据输出并且使能扫描数据输出。
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