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    Floating Body Memory Cell with a Non-Overlapping Gate Electrode
    4.
    发明申请
    Floating Body Memory Cell with a Non-Overlapping Gate Electrode 审中-公开
    具有非重叠栅电极的浮体记忆体

    公开(公告)号：US20090179262A1

    公开(公告)日：2009-07-16

    申请号：US12122135

    申请日：2008-05-16

    申请人： Juergen Holz ,  Wolfgang Mueller ,  Stefan Slesazeck

    发明人： Juergen Holz ,  Wolfgang Mueller ,  Stefan Slesazeck

    IPC分类号： H01L27/115 ,  H01L29/78

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827

    摘要： An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further includes a gate electrode adjacent to the third portion, the gate electrode being insulated from the third portion. The gate electrode does not overlap at least one of the first and second doped portions, and a line connecting the first and the second portions extends substantially perpendicular to a surface of the substrate.

    摘要翻译： 集成电路包括具有晶体管的存储单元。 晶体管包括第一和第二掺杂部分，以及设置在第一和第二掺杂部分之间的第三部分。 第一和第二掺杂部分和第三部分设置在半导体衬底中。 晶体管还包括与第三部分相邻的栅电极，栅电极与第三部分绝缘。 栅电极不与第一和第二掺杂部分中的至少一个重叠，并且连接第一和第二部分的线基本上垂直于衬底的表面延伸。

    Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor
    6.
    发明授权
    Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor 有权
    一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法

    公开(公告)号：US07189617B2

    公开(公告)日：2007-03-13

    申请号：US11105580

    申请日：2005-04-14

    申请人： Stefan Slesazeck ,  Alexander Sieck

    发明人： Stefan Slesazeck ,  Alexander Sieck

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7834 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66621

    摘要： The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

    摘要翻译： 本发明涉及一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法。 在一个实施例中，本发明使用衬底表面上的自调节间隔物来提供栅极和源极/漏极区域之间所需的距离。 因此，关于栅极接触平面中的光刻的公差的要求减弱。

    Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor
    7.
    发明申请
    Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor 有权
    一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法

    公开(公告)号：US20060234451A1

    公开(公告)日：2006-10-19

    申请号：US11105580

    申请日：2005-04-14

    申请人： Stefan Slesazeck ,  Alexander Sieck

    发明人： Stefan Slesazeck ,  Alexander Sieck

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7834 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66621

    摘要： The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

    摘要翻译： 本发明涉及一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法。 在一个实施例中，本发明使用衬底表面上的自调节间隔物来提供栅极和源极/漏极区域之间所需的距离。 因此，关于栅极接触平面中的光刻的公差的要求减弱。

    Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor
    8.
    发明授权
    Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor 有权
    包括晶闸管的集成电路和控制包括晶闸管的存储单元的方法

    公开(公告)号：US07940558B2

    公开(公告)日：2011-05-10

    申请号：US12339722

    申请日：2008-12-19

    申请人： Stefan Slesazeck

    发明人： Stefan Slesazeck

    IPC分类号： G11C11/36

    CPC分类号： G11C11/39

    摘要： An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.

    摘要翻译： 提供了一种集成电路，其包括分别由字线和位线连接的存储单元的阵列，其中每个存储单元包括晶闸管结构，将晶闸管结构与相应位线连接的阳极端子，连接晶闸管的栅极端子 具有相应字线的结构和阴极端子。 集成电路还包括被配置为在阳极端子和栅极端子处施加电压信号的第一序列的驱动/感测电路，其中相对于阴极端子限定电压信号。 第一序列包括在阳极端子处的第一电压信号，在栅极端子处的第二电压信号，然后在阳极端子处组合第三电压信号和栅极端子处的第四电压信号，其中第三电压信号 低于第一电压信号且低于第四电压信号。

    Memory Cell Array Comprising Floating Body Memory Cells
    10.
    发明申请
    Memory Cell Array Comprising Floating Body Memory Cells 有权
    包含浮动体记忆单元的记忆单元阵列

    公开(公告)号：US20090129145A1

    公开(公告)日：2009-05-21

    申请号：US11942330

    申请日：2007-11-19

    申请人： Stefan Slesazeck

    发明人： Stefan Slesazeck

    IPC分类号： G11C11/34 ,  G11C8/08 ,  G11C7/00

    CPC分类号： G11C8/14 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

    摘要： A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically connected to an individual memory cell of each pair of the cell rows.

    摘要翻译： 存储单元阵列包括布置在单元行和世界线中的多个浮体存储单元，其中每个字线被配置为控制与一对单元行对应的存储单元。 存储单元阵列还包括位线，其中每个位线电连接到每对单元行的单独存储单元。