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公开(公告)号：US07622354B2
公开(公告)日：2009-11-24
申请号：US11848857
申请日：2007-08-31
IPC分类号： H01L21/339
CPC分类号： H01L27/10876 , H01L21/84 , H01L21/86 , H01L27/10879 , H01L29/785
摘要： An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
摘要翻译： 包括存储器件的集成电路包括阵列部分，其包括存储器单元和导电线，导电线的上表面设置在半导体衬底的表面下方，以及支撑部分，包括第一类型的晶体管， 第一类型包括第一栅电极，该第一栅电极包括垂直于第一类型的晶体管的沟道垂直相邻的垂直部分。
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公开(公告)号：US20090057778A1
公开(公告)日：2009-03-05
申请号：US11848857
申请日：2007-08-31
IPC分类号： H01L27/085 , H01L21/8239
CPC分类号： H01L27/10876 , H01L21/84 , H01L21/86 , H01L27/10879 , H01L29/785
摘要： An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
摘要翻译： 包括存储器件的集成电路包括阵列部分，其包括存储器单元和导电线，导电线的上表面设置在半导体衬底的表面下方，以及支撑部分，包括第一类型的晶体管， 第一类型包括第一栅电极，该第一栅电极包括垂直于第一类型的晶体管的沟道垂直相邻的垂直部分。
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3.发明申请Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure 审中-公开用于形成凹陷沟道晶体管的制造方法，用于形成相应的集成半导体存储器件的方法和相应的自对准掩模结构公开(公告)号：US20080299722A1
公开(公告)日：2008-12-04
申请号：US11807550
申请日：2007-05-29
申请人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
发明人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L27/10876 , H01L29/4236 , H01L29/945
摘要： The present invention provides a method for forming a recessed channel transistor comprising the steps of: forming a plurality of active areas lines in a semiconductor substrate with an upper surface, said lines being segmented by segmentation structures having an upper surface height differing from the substrate surface; forming a first and a second extension region arranged above the active area and adjacent said segmentation structures; forming recessed channel devices in the active area segments in the remaining portion of the active area segment between said extension regions.
摘要翻译： 本发明提供了一种用于形成凹陷沟道晶体管的方法，包括以下步骤：在具有上表面的半导体衬底中形成多个有源区线，所述线被具有不同于衬底表面的上表面高度的分割结构分割 ; 形成布置在所述有效区域上方并邻近所述分割结构的第一和第二延伸区域; 在所述延伸区域之间的有源区段的剩余部分中的有源区段中形成凹陷通道器件。
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4.发明授权公开(公告)号：US07688660B2
公开(公告)日：2010-03-30
申请号：US11734433
申请日：2007-04-12
申请人： Stefan Slesazeck
发明人： Stefan Slesazeck
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C11/406 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state.
摘要翻译： 半导体存储器件包括耦合到具有晶体管的多个存储单元的电路。 电路被配置为根据身体的充电状态将晶体管的主体的电位改变到一定程度。 晶体管的栅电极保持在非寻址状态。
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公开(公告)号：US20090296449A1
公开(公告)日：2009-12-03
申请号：US12131802
申请日：2008-06-02
IPC分类号： G11C11/34
CPC分类号： G11C5/04 , G11C5/02 , G11C5/143 , G11C11/1673 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/76 , G11C2213/79
摘要： According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices.
摘要翻译： 根据本发明的一个实施例，提供一种集成电路，其包括多个电阻率变化存储元件和多个存储元件选择器件，其中所述选择器件是浮动体选择器件。
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公开(公告)号：US20090179262A1
公开(公告)日：2009-07-16
申请号：US12122135
申请日：2008-05-16
申请人： Juergen Holz , Wolfgang Mueller , Stefan Slesazeck
发明人： Juergen Holz , Wolfgang Mueller , Stefan Slesazeck
IPC分类号： H01L27/115 , H01L29/78
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/4236 , H01L29/42376 , H01L29/66666 , H01L29/7827
摘要： An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further includes a gate electrode adjacent to the third portion, the gate electrode being insulated from the third portion. The gate electrode does not overlap at least one of the first and second doped portions, and a line connecting the first and the second portions extends substantially perpendicular to a surface of the substrate.
摘要翻译： 集成电路包括具有晶体管的存储单元。 晶体管包括第一和第二掺杂部分，以及设置在第一和第二掺杂部分之间的第三部分。 第一和第二掺杂部分和第三部分设置在半导体衬底中。 晶体管还包括与第三部分相邻的栅电极，栅电极与第三部分绝缘。 栅电极不与第一和第二掺杂部分中的至少一个重叠，并且连接第一和第二部分的线基本上垂直于衬底的表面延伸。
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7.发明授权Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor 有权一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法公开(公告)号：US07189617B2
公开(公告)日：2007-03-13
申请号：US11105580
申请日：2005-04-14
申请人： Stefan Slesazeck , Alexander Sieck
发明人： Stefan Slesazeck , Alexander Sieck
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L21/28114 , H01L29/42376 , H01L29/6656 , H01L29/66621
摘要： The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.
摘要翻译： 本发明涉及一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法。 在一个实施例中，本发明使用衬底表面上的自调节间隔物来提供栅极和源极/漏极区域之间所需的距离。 因此，关于栅极接触平面中的光刻的公差的要求减弱。
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8.发明申请Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor 有权一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法公开(公告)号：US20060234451A1
公开(公告)日：2006-10-19
申请号：US11105580
申请日：2005-04-14
申请人： Stefan Slesazeck , Alexander Sieck
发明人： Stefan Slesazeck , Alexander Sieck
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L21/28114 , H01L29/42376 , H01L29/6656 , H01L29/66621
摘要： The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.
摘要翻译： 本发明涉及一种凹槽型阵列晶体管及相应的凹槽型阵列晶体管的制造方法。 在一个实施例中，本发明使用衬底表面上的自调节间隔物来提供栅极和源极/漏极区域之间所需的距离。 因此，关于栅极接触平面中的光刻的公差的要求减弱。
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9.发明授权Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor 有权包括晶闸管的集成电路和控制包括晶闸管的存储单元的方法公开(公告)号：US07940558B2
公开(公告)日：2011-05-10
申请号：US12339722
申请日：2008-12-19
申请人： Stefan Slesazeck
发明人： Stefan Slesazeck
IPC分类号： G11C11/36
CPC分类号： G11C11/39
摘要： An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.
摘要翻译： 提供了一种集成电路，其包括分别由字线和位线连接的存储单元的阵列，其中每个存储单元包括晶闸管结构，将晶闸管结构与相应位线连接的阳极端子，连接晶闸管的栅极端子 具有相应字线的结构和阴极端子。 集成电路还包括被配置为在阳极端子和栅极端子处施加电压信号的第一序列的驱动/感测电路，其中相对于阴极端子限定电压信号。 第一序列包括在阳极端子处的第一电压信号，在栅极端子处的第二电压信号，然后在阳极端子处组合第三电压信号和栅极端子处的第四电压信号，其中第三电压信号 低于第一电压信号且低于第四电压信号。
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10.发明申请Semiconductor Device, an Electronic Device and a Method for Operating the Same 审中-公开半导体器件，电子器件及其操作方法公开(公告)号：US20100014372A1
公开(公告)日：2010-01-21
申请号：US12572560
申请日：2009-10-02
申请人： Stefan Slesazeck
发明人： Stefan Slesazeck
CPC分类号： G11C11/4074 , G11C11/406 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a non-addressed state.
摘要翻译： 半导体存储器件包括耦合到具有晶体管的多个存储单元的电路。 电路被配置为根据身体的充电状态将晶体管的主体的电位改变到一定程度。 晶体管的栅电极保持在非寻址状态。
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