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公开(公告)号：US08195887B2
公开(公告)日：2012-06-05
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译： 公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。 当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。 如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。 在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。 因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。
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2.发明授权Determination of current stack pointer value using architectural and speculative stack pointer delta values 有权使用架构和推测堆栈指针增量值来确定当前堆栈指针值公开(公告)号：US07685406B2
公开(公告)日：2010-03-23
申请号：US11690029
申请日：2007-03-22
IPC分类号： G06F12/06
CPC分类号： G06F9/3842 , G06F9/30101 , G06F9/35 , G06F9/3824 , G06F9/3861
摘要： A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the stack dependent operation is determined. A stack pointer delta is then modified based upon the number of bytes associated with the stack dependent operation. A current location in the stack is determined based on the stack pointer and the stack pointer delta.
摘要翻译： 当遇到与堆栈相关的指令对应的堆栈相关操作时，减少堆栈指针调整操作的技术包括将堆栈指针设置为堆栈的初始值。 确定与堆栈相关操作相关联的多个字节。 然后基于与堆栈依赖操作相关联的字节数来修改堆栈指针增量。 基于堆栈指针和堆栈指针delta来确定堆栈中的当前位置。
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3.发明授权Controlling writes to non-renamed register space in an out-of-order execution microprocessor 有权控制对无序执行微处理器中的未重命名寄存器空间的写入公开(公告)号：US07373484B1
公开(公告)日：2008-05-13
申请号：US10755692
申请日：2004-01-12
申请人： Arun Radhakrishnan , Benjamin T. Sander , Michael A. Filippo , Michael T. Clark , David E. Kroesche
发明人： Arun Radhakrishnan , Benjamin T. Sander , Michael A. Filippo , Michael T. Clark , David E. Kroesche
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3013 , G06F9/384
摘要： A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.
摘要翻译： 控制对未重新命名的寄存器空间的写入操作的方法包括：接收对非重命名寄存器空间内的给定寄存器的写操作。 该方法还包括确定是否存在对给定寄存器的挂起写入操作。 响应于确定对给定寄存器的挂起写入操作存在，该方法包括阻止对给定寄存器的写入操作被调度。 然而，响应于确定对给定寄存器的挂起写操作不存在，该方法包括允许对给定寄存器的写操作进行调度。 此外，如果对给定寄存器的挂起写入操作不存在，则该方法包括允许对未重新命名的寄存器空间内的不同寄存器的后续写入操作进行调度。
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4.发明授权Speculation pointers to identify data-speculative operations in microprocessor 有权用于识别微处理器中数据推测操作的推测指针公开(公告)号：US07266673B2
公开(公告)日：2007-09-04
申请号：US10429159
申请日：2003-05-02
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3865
摘要： A microprocessor may include a retire queue and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation pointer identifying outstanding operations on which data speculation has been verified by that data speculation verification unit. The retire queue is configured to selectively retire operations dependent on the speculation pointer received from each of the data speculation verification units.
摘要翻译： 微处理器可以包括退出队列和一个或多个数据推测验证单元。 数据推测验证单元被配置为验证对操作执行的数据推测。 每个数据推测验证单元产生识别由该数据推测验证单元已经对其进行数据猜测的未完成操作的各个推测指针。 退休队列被配置为根据从每个数据推测验证单元接收的推测指针选择性地退出操作。
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5.发明授权System and method for validating a memory file that links speculative results of load operations to register values 有权用于验证将加载操作的推测结果链接到寄存器值的存储器文件的系统和方法公开(公告)号：US07263600B2
公开(公告)日：2007-08-28
申请号：US10839474
申请日：2004-05-05
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3826 , G06F9/383 , G06F9/3832 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： A system and method for linking speculative results of load operations to register values. A system includes a memory file including an entry configured to store a first addressing pattern and a first tag. The memory file is configured to compare the first addressing pattern to a second addressing pattern of a load operation, and to link a data value identified by the first tag to a speculative result of the load operation if there is a match. The system further includes an execution core coupled to the memory file and configured to access the speculative result when executing a second operation that is dependent on the load operation, and a load store unit coupled to the memory file and configured to verify the link between the data value and the speculative result of the load operation by performing a comparison between one or more addresses.
摘要翻译： 一种用于将加载操作的推测结果与寄存器值相关联的系统和方法。 系统包括存储器文件，其包括被配置为存储第一寻址模式和第一标签的条目。 存储器文件被配置为将第一寻址模式与加载操作的第二寻址模式进行比较，并且如果存在匹配，则将由第一标签识别的数据值链接到加载操作的推测结果。 所述系统还包括耦合到所述存储器文件并且被配置为在执行取决于所述加载操作的第二操作时访问所述推测结果的执行核心，以及耦合到所述存储器文件并被配置为验证所述 数据值和通过执行一个或多个地址之间的比较的加载操作的推测结果。
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公开(公告)号：US07165167B2
公开(公告)日：2007-01-16
申请号：US10458457
申请日：2003-06-10
IPC分类号： G06F9/24
CPC分类号： G06F9/3842 , G06F9/3826 , G06F9/3832 , G06F9/3834 , G06F9/3861
摘要： A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
摘要翻译： 微处理器可以包括被配置为发布操作的调度器和被配置为执行由调度器发出的存储器操作的加载存储单元。 加载存储单元被配置为存储识别发送到加载存储单元的存储器操作的信息。 响应于检测到所发出的存储器操作之一的不正确的数据推测，加载存储单元被配置为通过向调度器提供指示来重播所发布的存储器操作中的至少一个。 调度器被配置为响应地重新发出由加载存储单元识别的存储器操作。
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公开(公告)号：US07133995B1
公开(公告)日：2006-11-07
申请号：US10320034
申请日：2002-12-16
申请人： Roger Isaac , Benjamin T. Sander
发明人： Roger Isaac , Benjamin T. Sander
IPC分类号： G06F12/00
CPC分类号： G06F12/0215
摘要： A memory controller may be implemented using dynamic page conflict prediction to control the closure of memory pages. A memory controller may include a page history register configured to store a value indicating the pattern of page conflicts encountered by a memory device. The memory controller may include a global conflict predictor for storing probabilities of page conflicts associated with values of the page history register. In response to receiving a memory access request, a control unit may be configured to determine whether the memory access request causes a page conflict. The memory controller may be configured to update the global conflict predictor based on this determination. If a page conflict is predicted, the memory controller may automatically close the targeted page (e.g., by initiating the memory access in auto-precharge mode) upon completion of the memory access requested by the memory access request.
摘要翻译： 可以使用动态页面冲突预测实现存储器控制器以控制存储器页面的关闭。 存储器控制器可以包括被配置为存储指示存储器设备遇到的页面冲突的模式的值的页历史寄存器。 存储器控制器可以包括用于存储与页历史寄存器的值相关联的页冲突的概率的全局冲突预测器。 响应于接收到存储器访问请求，控制单元可以被配置为确定存储器访问请求是否引起页冲突。 存储器控制器可以被配置为基于该确定来更新全局冲突预测器。 如果预测到页面冲突，则存储器控制器可以在存储器访问请求所请求的存储器访问完成时自动关闭目标页面（例如，通过在自动预充电模式中启动存储器访问）。
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8.发明授权Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism 有权基于Stride的预取器，具有置信度计数器和动态预取提前机制公开(公告)号：US06571318B1
公开(公告)日：2003-05-27
申请号：US09798469
申请日：2001-03-02
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry includes a confidence counter. The confidence counter may be incremented each time another address in the pattern is detected, and thus may be indicative of the strength of the pattern (e.g., the likelihood of the pattern repeating). At a first threshold of the confidence counter, prefetching of the next address in the pattern (the most recent address plus the stride) may be initiated. At a second, greater threshold, a more aggressive prefetching may be initiated (e.g. the most recent address plus twice the stride). In some implementations, the prefetch mechanism including the stride detect table may replace a prefetch buffer and prefetch logic in the memory controller.
摘要翻译： 描述了包括步幅检测表的处理器。 步幅检测表包括一个或多个条目，每个条目用于跟踪潜在的步幅图案。 另外，每个条目都包含一个置信计数器。 每次检测到图案中的另一个地址时，置信度计数器可以递增，因此可以指示图案的强度（例如，图案重复的可能性）。 在置信计数器的第一阈值处，可以启动模式中的下一个地址（最近的地址加大步）的预取。 在第二个更大的阈值下，可以启动更积极的预取（例如，最近的地址加上步幅的两倍）。 在一些实现中，包括步幅检测表的预取机制可以替代存储器控制器中的预取缓冲器和预取逻辑。
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公开(公告)号：US20110066811A1
公开(公告)日：2011-03-17
申请号：US12558465
申请日：2009-09-11
CPC分类号： G06F12/0862 , G06F12/0815 , G06F2212/6026
摘要： A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor detects a data stream by identifying a sequence of storage accesses referencing a contiguous blocks of data in a monotonically increasing or decreasing manner. After a predetermined training period for a given data stream, the prefetch unit prefetches a portion of the given data stream from memory without write permission, in response to an access that does not request write permission. Also, after the training period, the prefetch unit prefetches a portion of the given data stream from lower-level memory with write permission, in response to determining there has been a prior access to the given data stream that requests write permission subsequent to a number of cache misses reaching a predetermined threshold.
摘要翻译： 一种用于高效数据预取的系统和方法。 存储在下级存储器中的数据流包括在计算机程序中使用的连续的数据块。 处理器中的预取单元通过以单调递增或递减的方式识别参考连续数据块的存储访问序列来检测数据流。 在针对给定数据流的预定训练周期之后，响应于不请求写许可的访问，预取单元从存储器中预取给定数据流的一部分而不具有写许可。 此外，在训练期之后，预取单元响应于确定先前访问给定数据流的请求后的写入权限，从而从具有写许可的下级存储器中预取给定数据流的一部分 的高速缓存未命中达到预定阈值。
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公开(公告)号：US20100185820A1
公开(公告)日：2010-07-22
申请号：US12356624
申请日：2009-01-21
申请人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
发明人： William A. Hughes , Kiran K. Bondalapati , Vydhyanathan Kalyanasundharam , Kevin M. Lepak , Benjamin T. Sander
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F12/0808 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D50/20
摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
摘要翻译： 公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。 当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。 如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。 在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。 因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。
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