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公开(公告)号：US20120023314A1
公开(公告)日：2012-01-26
申请号：US12840835
申请日：2010-07-21
CPC分类号： G06F9/3838 , G06F9/3826
摘要： A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior to a scheduling pipe stage. For each data dependency, a distance value is determined based on a number of instructions a younger dependent instruction is located from a corresponding older (in program order) instruction. When the younger dependent instruction is allocated an entry in a multi-cycle scheduler, this distance value may be used to locate an entry storing the older instruction in the scheduler. When the older instruction is picked for issue, the younger dependent instruction is marked as pre-picked. In an immediately subsequent clock cycle, the younger dependent instruction may be picked for issue, thereby reducing the latency of the multi-cycle scheduler.
摘要翻译： 一种用于减少处理器内的多周期调度器的等待时间的方法和机制。 处理器包括前端流水线，其在调度管道级之前确定指令之间的数据依赖性。 对于每个数据依赖性，基于较年轻的依赖指令从相应的较旧（在程序顺序）指令中定位的指令的数量来确定距离值。 当在多循环调度器中分配较年轻的依赖指令时，该距离值可以用于定位存储在调度器中的旧指令的条目。 当较老的指令被挑选出来时，年龄较大的指令被标记为预选。 在随后的时钟周期中，可以挑选较年轻的依赖指令以进行发布，从而减少多周期调度器的等待时间。
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公开(公告)号：US07043544B2
公开(公告)日：2006-05-09
申请号：US10029703
申请日：2001-12-21
IPC分类号： G06F15/16
CPC分类号： H04L29/06 , H04L49/103 , H04L49/30 , H04L69/22
摘要： A network processor or other type of processor includes classification circuitry and memory circuitry coupled to the classification circuitry. The memory circuitry is configured to store at least a portion of at least a given one of a number of packets to be processed by the classification circuitry. The classification circuitry implements a non-sequential packet classification process for at least a subset of the packets including the given packet. For example, in an embodiment in which the given packet is generated in accordance with multiple embedded protocols, the non-sequential packet classification process allows the processor to return from a given point within the packet, at which a final one of the protocols is identified, to a beginning of the packet, through the use of a “skip to beginning” instruction. The skip to beginning instruction may be configured to allow the processor to skip back to a particular bit, e.g., a first bit, of the given packet at a time during the classification process after which the particular bit has been processed, such that multiple passes of the classification process can be performed on the given packet. The processor may be configured as a network processor integrated circuit to provide an interface between a network from which the packet is received and a switch fabric in a router or switch.
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3.发明授权公开(公告)号：US07079539B2
公开(公告)日：2006-07-18
申请号：US10029705
申请日：2001-12-21
CPC分类号： H04L49/30 , H04L49/103
摘要： A network processor or other type of processor includes in an illustrative embodiment a first pass classifier coupled to first memory circuitry in the form of a relatively small internal memory, and a second pass classifier coupled to second memory circuitry in the form of a larger internal buffer memory. The first memory circuitry is configurable to store at least a portion of a given packet to be processed by the first pass classifier. The second memory circuitry is configurable to store a different and preferably smaller portion of the given packet to permit processing thereof by the second pass classifier. The portion of the given packet storable in the second memory circuitry is a portion of the given packet determined by a first pass classification, performed by the first pass classifier, to be required for a second pass classification, performed by the second pass classifier. Advantageously, the invention reduces the size of the packet portion required to be stored in the second memory circuitry, thereby reducing the required memory of the processor. The processor may be configured as a network processor integrated circuit to provide an interface between a network from which the packet is received and a switch fabric in a router or switch.
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公开(公告)号：US06915480B2
公开(公告)日：2005-07-05
申请号：US10029704
申请日：2001-12-21
CPC分类号： H04L1/201 , H04L1/0061 , H04L1/0082 , H04L2001/0092
摘要： A network processor or other type of processor includes first classification circuitry, scheduling circuitry and second classification circuitry. The first classification circuitry is configured to determine for a given packet received by the processor whether the packet has one or more errors. The scheduling circuitry in an illustrative embodiment receives an indication of the error determination made by the first classification circuitry, and based on the indication controls the dropping of the given packet from the processor memories if the packet has one or more errors, e.g., via a flush transmit command. The second classification circuitry, which may be implemented as a single classification engine or a set of such engines, may be configured to perform at least one classification operation for the given packet, e.g., if the packet is supplied thereto by the scheduling circuitry.
摘要翻译： 网络处理器或其他类型的处理器包括第一分类电路，调度电路和第二分类电路。 第一分类电路被配置为确定由处理器接收到的给定分组数据包是否具有一个或多个错误。 说明性实施例中的调度电路接收由第一分类电路作出的错误确定的指示，并且如果分组具有一个或多个错误，则基于该指示控制来自处理器存储器的给定分组的丢弃，例如，经由 flush发送命令。 可以被实现为单个分类引擎或一组这样的引擎的第二分类电路可以被配置为对给定分组执行至少一个分类操作，例如，如果分组被调度电路提供给它。
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5.发明授权Method of improving the lookup performance of three-type knowledge base searches 有权提高三类知识库搜索查找性能的方法公开(公告)号：US07246102B2
公开(公告)日：2007-07-17
申请号：US10037040
申请日：2001-12-21
申请人： Betty A. McDaniel , William Edward Baker , Narender R. Vangati , Mauricio Calle , James T. Kirk
发明人： Betty A. McDaniel , William Edward Baker , Narender R. Vangati , Mauricio Calle , James T. Kirk
CPC分类号： G06N5/02 , Y10S706/934 , Y10S707/99942
摘要： A decision tree, representing a knowledge base, is segmented into at least two decision tree portions. The lower portion includes the tree entry point and is stored in a memory element with a faster access time than the upper portion, which includes the terminating element of the decision tree. Thus during the process of reading the tree entries for comparing them with the search object, the search entries in the lower portion of the tree can be read faster than the search entries in the upper portion, resulting in a faster traversal through the entire decision tree.
摘要翻译： 代表知识库的决策树被分割成至少两个决策树部分。 下部包括树入口点，并且被存储在具有比包括决策树的终止元素的上部更快的访问时间的存储元件中。 因此，在读取用于将它们与搜索对象进行比较的树条目的过程中，树的下部的搜索条目可以比上部的搜索条目更快地读取，导致通过整个决策树的更快的遍历 。
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