PAIRED EXECUTION SCHEDULING OF DEPENDENT MICRO-OPERATIONS
    1.
    发明申请
    PAIRED EXECUTION SCHEDULING OF DEPENDENT MICRO-OPERATIONS 审中-公开
    配对执行依赖性微操作

    公开(公告)号:US20120023314A1

    公开(公告)日:2012-01-26

    申请号:US12840835

    申请日:2010-07-21

    IPC分类号: G06F9/30 G06F9/38

    CPC分类号: G06F9/3838 G06F9/3826

    摘要: A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior to a scheduling pipe stage. For each data dependency, a distance value is determined based on a number of instructions a younger dependent instruction is located from a corresponding older (in program order) instruction. When the younger dependent instruction is allocated an entry in a multi-cycle scheduler, this distance value may be used to locate an entry storing the older instruction in the scheduler. When the older instruction is picked for issue, the younger dependent instruction is marked as pre-picked. In an immediately subsequent clock cycle, the younger dependent instruction may be picked for issue, thereby reducing the latency of the multi-cycle scheduler.

    摘要翻译: 一种用于减少处理器内的多周期调度器的等待时间的方法和机制。 处理器包括前端流水线,其在调度管道级之前确定指令之间的数据依赖性。 对于每个数据依赖性,基于较年轻的依赖指令从相应的较旧(在程序顺序)指令中定位的指令的数量来确定距离值。 当在多循环调度器中分配较年轻的依赖指令时,该距离值可以用于定位存储在调度器中的旧指令的条目。 当较老的指令被挑选出来时,年龄较大的指令被标记为预选。 在随后的时钟周期中,可以挑选较年轻的依赖指令以进行发布,从而减少多周期调度器的等待时间。

    Way preparation for accessing a cache
    2.
    发明授权
    Way preparation for accessing a cache 有权
    准备访问缓存的方式

    公开(公告)号:US09256544B2

    公开(公告)日:2016-02-09

    申请号:US13726825

    申请日:2012-12-26

    IPC分类号: G06F12/08 G06F1/32

    摘要: For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

    摘要翻译: 对于在处理器处的存储器访问,仅准备存储器与存储器地址相关联的高速缓存的一个子集(少于全部)以进行访问。 基于存储的信息来选择方法的子集,该信息指示对于每个存储器访问,哪个高速缓存的相应方式被访问。 选择方法的子集,并且在最终确定要在子集中访问哪个单独缓存方式之前启动方法子集的准备。