公开(公告)号：US09256544B2

公开(公告)日：2016-02-09

申请号：US13726825

申请日：2012-12-26

申请人： Matthew M. Crum ,  Teik-Chung Tan

发明人： Matthew M. Crum ,  Teik-Chung Tan

IPC分类号： G06F12/08 ,  G06F1/32

CPC分类号： G06F12/0895 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

摘要翻译： 对于在处理器处的存储器访问，仅准备存储器与存储器地址相关联的高速缓存的一个子集（少于全部）以进行访问。 基于存储的信息来选择方法的子集，该信息指示对于每个存储器访问，哪个高速缓存的相应方式被访问。 选择方法的子集，并且在最终确定要在子集中访问哪个单独缓存方式之前启动方法子集的准备。

公开(公告)号：US20120023314A1

公开(公告)日：2012-01-26

申请号：US12840835

申请日：2010-07-21

申请人： Matthew M. Crum ,  Michael D. Achenbach ,  Betty A. McDaniel ,  Benjamin T. Sander

发明人： Matthew M. Crum ,  Michael D. Achenbach ,  Betty A. McDaniel ,  Benjamin T. Sander

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3826

摘要： A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior to a scheduling pipe stage. For each data dependency, a distance value is determined based on a number of instructions a younger dependent instruction is located from a corresponding older (in program order) instruction. When the younger dependent instruction is allocated an entry in a multi-cycle scheduler, this distance value may be used to locate an entry storing the older instruction in the scheduler. When the older instruction is picked for issue, the younger dependent instruction is marked as pre-picked. In an immediately subsequent clock cycle, the younger dependent instruction may be picked for issue, thereby reducing the latency of the multi-cycle scheduler.

摘要翻译： 一种用于减少处理器内的多周期调度器的等待时间的方法和机制。 处理器包括前端流水线，其在调度管道级之前确定指令之间的数据依赖性。 对于每个数据依赖性，基于较年轻的依赖指令从相应的较旧（在程序顺序）指令中定位的指令的数量来确定距离值。 当在多循环调度器中分配较年轻的依赖指令时，该距离值可以用于定位存储在调度器中的旧指令的条目。 当较老的指令被挑选出来时，年龄较大的指令被标记为预选。 在随后的时钟周期中，可以挑选较年轻的依赖指令以进行发布，从而减少多周期调度器的等待时间。

公开(公告)号：US20120005459A1

公开(公告)日：2012-01-05

申请号：US12979948

申请日：2010-12-28

申请人： Jay FLEISCHMAN ,  Matthew M. CRUM ,  Michael ESTLICK ,  Ranganathan SUDHAKAR ,  Emil TALPES ,  Ganesh VENKATARAMANAN ,  Barry J. Arnold ,  Michael Sedmak

发明人： Jay FLEISCHMAN ,  Matthew M. CRUM ,  Michael ESTLICK ,  Ranganathan SUDHAKAR ,  Emil TALPES ,  Ganesh VENKATARAMANAN ,  Barry J. Arnold ,  Michael Sedmak

IPC分类号： G06F9/30

CPC分类号： G06F9/384 ,  G06F9/30032 ,  G06F9/3017

摘要： Methods and apparatuses are provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The apparatus comprises a first plurality of available physical registers mapped to a second plurality of logical registers, including a source logical register and a destination logical register. A renaming unit remaps the destination logical register to the same physical register mapping as the source logical register in response to a move instruction. In this way, the move instruction is effectively executed without moving data between physical registers. A method is provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The method comprises determining a mapping of a logical source register and a logical destination register to physical registers of a processor and then remapping the logical destination register to the same physical register mapping as the logical source register to affect an equivalent of the move instruction with actual data movement between physical registers.

摘要翻译： 提供了通过消除物理数据移动来实现移动指令来提高处理器性能和节能的方法和装置。 该装置包括映射到包括源逻辑寄存器和目的地逻辑寄存器的第二多个逻辑寄存器的第一多个可用物理寄存器。 重命名单元将目的地逻辑寄存器重新映射到与源逻辑寄存器相同的物理寄存器映射以响应移动指令。 以这种方式，在不在物理寄存器之间移动数据的情况下，有效地执行移动指令。 提供了一种通过消除物理数据移动来实现移动指令来提高处理器性能和节能的方法。 该方法包括确定逻辑源寄存器和逻辑目标寄存器到处理器的物理寄存器的映射，然后将逻辑目标寄存器重映射到与逻辑源寄存器相同的物理寄存器映射，以影响具有实际值的移位指令的等效值 物理寄存器之间的数据移动。

公开(公告)号：US20120191952A1

公开(公告)日：2012-07-26

申请号：US13011637

申请日：2011-01-21

申请人： Jay E. FLEISCHMAN ,  Matthew M. CRUM ,  Kelvin GOVEAS ,  Michael D. ESTLICK ,  Barry J. ARNOLD ,  Ranganathan SUDHAKAR ,  Betty A. MCDANIEL

发明人： Jay E. FLEISCHMAN ,  Matthew M. CRUM ,  Kelvin GOVEAS ,  Michael D. ESTLICK ,  Barry J. ARNOLD ,  Ranganathan SUDHAKAR ,  Betty A. MCDANIEL

IPC分类号： G06F9/318 ,  G06F9/30

CPC分类号： G06F9/30094 ,  G06F9/30109 ,  G06F9/30192 ,  G06F9/384

摘要： Methods and apparatuses are provided for increased efficiency and enhanced power saving in a processor via scalar code optimization. The method comprises determining that an instruction comprises a scalar instruction and then processing the instruction using only a lower portion of an XMM register. The apparatus comprises an operational unit capable of determining whether an instruction comprises a scalar instruction and execution units responsive that determining for processing the scalar instruction using only a lower portion of an XMM register of the processor. By not processing the upper portion of the XMM register efficiency is increased and power saving is enhanced.

摘要翻译： 提供了通过标量代码优化在处理器中提高效率和增强功率节省的方法和装置。 该方法包括确定指令包括标量指令，然后仅使用XMM寄存器的下部来处理该指令。 所述装置包括能够确定指令是否包括标量指令的操作单元，并且所述执行单元响应于仅使用所述处理器的XMM寄存器的下部来确定所述标量指令的处理。 通过不处理XMM寄存器的上部部分，效率提高，省电。