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公开(公告)号：US08642419B2
公开(公告)日：2014-02-04
申请号：US13400407
申请日：2012-02-20
IPC分类号： H01L21/8238
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.
摘要翻译： 本文公开了形成用于半导体器件的隔离结构，例如沟槽隔离结构的各种方法。 在一个示例中，该方法包括在半导体衬底中形成沟槽，在沟槽中形成较低的隔离结构，其中下部隔离结构具有位于衬底上表面下方的上表面，并且形成上部隔离结构 所述下隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。
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2.发明申请METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL 审中-公开通过使用旋转玻璃材料或可流动的氧化物材料形成半导体器件的隔离结构的方法公开(公告)号：US20130221478A1
公开(公告)日：2013-08-29
申请号：US13405713
申请日：2012-02-27
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices using a spin-on glass material or a flowable oxide material. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure comprised of an insulating material in at least the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.
摘要翻译： 本文公开了用于使用旋涂玻璃材料或可流动氧化物材料的半导体器件形成隔离结构（例如沟槽隔离结构）的各种方法。 在一个示例中，该方法包括在半导体衬底中形成沟槽，在至少沟槽中形成由绝缘材料构成的下隔离结构，其中下隔离结构具有位于衬底上表面下方的上表面， 以及在所述下隔离结构之上形成上隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。
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3.发明申请METHODS OF FORMING STEPPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES USING A SPACER TECHNIQUE 审中-公开使用间隔技术形成半导体器件的步进隔离结构的方法公开(公告)号：US20130214392A1
公开(公告)日：2013-08-22
申请号：US13400422
申请日：2012-02-20
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming stepped isolation structures for semiconductor devices using a spacer technique. In one example, the method includes forming a first trench in a semiconducting substrate, wherein the first trench has a bottom surface, a width and a depth, the depth of the first trench being less than a target final depth for a stepped trench isolation structure, performing an etching process through the first trench on an exposed portion of the bottom surface of the first trench to form a second trench in the substrate, wherein the second trench has a width and a depth, and wherein the width of the second trench is less than the width of the first trench, and forming the stepped isolation structure in the first and second trenches.
摘要翻译： 本文公开了使用间隔物技术形成用于半导体器件的阶梯式隔离结构的各种方法。 在一个示例中，该方法包括在半导体衬底中形成第一沟槽，其中第一沟槽具有底表面，宽度和深度，第一沟槽的深度小于阶梯式沟槽隔离结构的目标最终深度 ，在所述第一沟槽的底表面的暴露部分上通过所述第一沟槽进行蚀刻处理，以在所述衬底中形成第二沟槽，其中所述第二沟槽具有宽度和深度，并且其中所述第二沟槽的宽度为 小于第一沟槽的宽度，并且在第一和第二沟槽中形成阶梯式隔离结构。
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公开(公告)号：US20130214381A1
公开(公告)日：2013-08-22
申请号：US13400407
申请日：2012-02-20
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.
摘要翻译： 本文公开了形成用于半导体器件的隔离结构（例如沟槽隔离结构）的各种方法。 在一个示例中，该方法包括在半导体衬底中形成沟槽，在沟槽中形成较低的隔离结构，其中下部隔离结构具有位于衬底上表面下方的上表面，并且形成上部隔离结构 所述下隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。
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5.发明授权Methods of forming PEET devices with different structures and performance characteristics 有权形成具有不同结构和性能特征的PFET器件的方法公开(公告)号：US08735303B2
公开(公告)日：2014-05-27
申请号：US13287403
申请日：2011-11-02
IPC分类号： H01L21/31
CPC分类号： H01L27/088 , H01L21/823412 , H01L27/108 , H01L27/10894 , H01L29/1033
摘要： One illustrative method disclosed herein includes forming a first recess in a first active region of a substrate, forming a first layer of channel semiconductor material for a first PFET transistor in the first recess, performing a first thermal oxidation process to form a first protective layer on the first layer of channel semiconductor material, forming a second recess in the second active region of the semiconducting substrate, forming a second layer of channel semiconductor material for the second PFET transistor in the second recess and performing a second thermal oxidation process to form a second protective layer on the second layer of channel semiconductor material.
摘要翻译： 本文公开的一种说明性方法包括在衬底的第一有源区中形成第一凹槽，在第一凹槽中形成用于第一PFET晶体管的沟道半导体材料的第一层，执行第一热氧化工艺以形成第一保护层 所述第一沟道半导体材料层在所述半导体衬底的所述第二有源区中形成第二凹槽，在所述第二凹槽中形成用于所述第二PFET晶体管的沟道半导体材料的第二层，并执行第二热氧化工艺以形成第二层 沟道半导体材料的第二层上的保护层。
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公开(公告)号：US08796080B2
公开(公告)日：2014-08-05
申请号：US13287466
申请日：2011-11-02
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/76232 , H01L29/1054 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： Disclosed herein are various methods of epitaxially forming materials on transistor devices. In one example, the method includes forming an isolation region in a semiconducting substrate that defines an active area, performing a heating process on the active area to cause an upper surface of the active area to become a curved surface and performing an etching process on the active area to define a recess having a curved bottom surface. The method further includes the steps of forming a channel semiconductor material in the recess with a curved upper surface and forming a gate structure for a transistor above the curved upper surface of the channel semiconductor material.
摘要翻译： 本文公开了在晶体管器件上外延形成材料的各种方法。 在一个示例中，该方法包括在限定有源区域的半导体衬底中形成隔离区域，在有源区域上执行加热处理，以使有源区域的上表面变成曲面，并且对 活动区域以限定具有弯曲底面的凹部。 该方法还包括以下步骤：在具有弯曲的上表面的凹槽中形成沟道半导体材料，并在通道半导体材料的弯曲上表面上形成用于晶体管的栅极结构。
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7.发明申请Methods of Forming PFET Devices With Different Structures and Performance Characteristics 有权形成具有不同结构和性能特征的PFET器件的方法公开(公告)号：US20130105900A1
公开(公告)日：2013-05-02
申请号：US13287403
申请日：2011-11-02
IPC分类号： H01L27/088 , H01L21/20
CPC分类号： H01L27/088 , H01L21/823412 , H01L27/108 , H01L27/10894 , H01L29/1033
摘要： One illustrative method disclosed herein includes forming a first recess in a first active region of a substrate, forming a first layer of channel semiconductor material for a first PFET transistor in the first recess, performing a first thermal oxidation process to form a first protective layer on the first layer of channel semiconductor material, forming a second recess in the second active region of the semiconducting substrate, forming a second layer of channel semiconductor material for the second PFET transistor in the second recess and performing a second thermal oxidation process to form a second protective layer on the second layer of channel semiconductor material.
摘要翻译： 本文公开的一种说明性方法包括在衬底的第一有源区中形成第一凹槽，在第一凹槽中形成用于第一PFET晶体管的沟道半导体材料的第一层，执行第一热氧化工艺以形成第一保护层 所述第一沟道半导体材料层在所述半导体衬底的所述第二有源区中形成第二凹槽，在所述第二凹槽中形成用于所述第二PFET晶体管的沟道半导体材料的第二层，并执行第二热氧化工艺以形成第二层 沟道半导体材料的第二层上的保护层。
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公开(公告)号：US20130105917A1
公开(公告)日：2013-05-02
申请号：US13287466
申请日：2011-11-02
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/76232 , H01L29/1054 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： Disclosed herein are various methods of epitaxially forming materials on transistor devices. In one example, the method includes forming an isolation region in a semiconducting substrate that defines an active area, performing a heating process on the active area to cause an upper surface of the active area to become a curved surface and performing an etching process on the active area to define a recess having a curved bottom surface. The method further includes the steps of forming a channel semiconductor material in the recess with a curved upper surface and forming a gate structure for a transistor above the curved upper surface of the channel semiconductor material.
摘要翻译： 本文公开了在晶体管器件上外延形成材料的各种方法。 在一个示例中，该方法包括在限定有源区域的半导体衬底中形成隔离区域，在有源区域上执行加热处理，以使有源区域的上表面变成曲面，并且对 活动区域以限定具有弯曲底面的凹部。 该方法还包括以下步骤：在具有弯曲的上表面的凹槽中形成沟道半导体材料，并在通道半导体材料的弯曲上表面上形成用于晶体管的栅极结构。
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9.发明申请Method of Protecting STI Structures From Erosion During Processing Operations 有权保护STI结构防止加工操作过程中侵蚀的方法公开(公告)号：US20120302037A1
公开(公告)日：2012-11-29
申请号：US13115270
申请日：2011-05-25
IPC分类号： H01L21/762
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807 , H01L21/823842 , H01L21/84 , H01L27/10894 , H01L27/1203
摘要： Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.
摘要翻译： 通常，本公开涉及一种在制造期间至少减少半导体器件的隔离结构的不希望的侵蚀的方法。 所公开的一种说明性方法包括在半导体衬底中形成隔离结构，并在多个隔离结构之上形成导电保护环。
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10.发明申请High-K Metal Gate Electrode Structures Formed by Cap Layer Removal Without Sacrificial Spacer 有权高K金属栅电极结构由盖层去除而没有牺牲间隔物公开(公告)号：US20120161243A1
公开(公告)日：2012-06-28
申请号：US13198107
申请日：2011-08-04
IPC分类号： H01L27/092 , H01L21/8234
CPC分类号： H01L21/823864 , H01L21/31116 , H01L21/31155 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.
摘要翻译： 在复杂的半导体器件中，高k金属栅极电极结构可以在早期制造阶段形成，其中敏感栅极材料的完整性通过在选定的活性区域中选择性沉积应变诱导半导体材料之后提供附加的衬垫材料。 此外，可以基于通过避免图案化和去除任何牺牲氧化物间隔物而显着降低隔离区域和有源区域中的材料侵蚀程度的工艺流程来去除栅电极结构的电介质盖材料。
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