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    EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER
    1.
    发明申请
    EARLY EMBEDDED SILICON GERMANIUM WITH INSITU BORON DOPING AND OXIDE/NITRIDE PROXIMITY SPACER 有权
    早期嵌入式硅锗，含有硼酸盐和氧化物/硝酸盐邻近间隔物

    公开(公告)号：US20120267683A1

    公开(公告)日：2012-10-25

    申请号：US13089799

    申请日：2011-04-19

    申请人： Stephan Kronholz ,  Matthias Kessler ,  Ricardo Mikalo

    发明人： Stephan Kronholz ,  Matthias Kessler ,  Ricardo Mikalo

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  B82Y99/00 ,  B82Y40/00

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.

    摘要翻译： 在形成eSiGe间隔物之前，器件由氧化物衬垫和氮化物层形成。 实施例包括在衬底上形成第一和第二栅极堆叠，在第一和第二栅极堆叠上形成氧化物衬垫，在氧化物衬底上形成氮化物层，在第一栅极堆叠上形成抗蚀剂，在氮化物层上形成氮化物间隔物， 形成用于第二栅极堆叠的eSiGe源极/漏极区域，随后形成用于第一栅极堆叠的卤素/延伸区域，并且独立地形成用于第二栅极叠层的卤素/延伸区域。 实施例包括通过使用氮化物间隔物作为软掩模，用TMAH湿蚀刻衬底来形成eSiGe区域，形成σ形空腔，以及在空腔中外延生长的硼掺杂eSiGe。

    Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer
    2.
    发明授权
    Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer 有权
    早期嵌入式硅锗，具有原位硼掺杂和氧化物/氮化物接近间隔物

    公开(公告)号：US08334185B2

    公开(公告)日：2012-12-18

    申请号：US13089799

    申请日：2011-04-19

    申请人： Stephan Kronholz ,  Matthias Kessler ,  Ricardo Mikalo

    发明人： Stephan Kronholz ,  Matthias Kessler ,  Ricardo Mikalo

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.

    摘要翻译： 在形成eSiGe间隔物之前，器件由氧化物衬垫和氮化物层形成。 实施例包括在衬底上形成第一和第二栅极堆叠，在第一和第二栅极堆叠上形成氧化物衬垫，在氧化物衬底上形成氮化物层，在第一栅极堆叠上形成抗蚀剂，在氮化物层上形成氮化物间隔物， 形成用于第二栅极堆叠的eSiGe源极/漏极区域，随后形成用于第一栅极堆叠的卤素/延伸区域，并且独立地形成用于第二栅极叠层的卤素/延伸区域。 实施例包括通过使用氮化物间隔物作为软掩模，用TMAH湿蚀刻衬底来形成eSiGe区域，形成σ形空腔，以及在空腔中外延生长的硼掺杂eSiGe。

    Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode
    4.
    发明授权
    Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode 有权
    晶体管包括在栅极电极下方延伸的漏极和源极区域中的嵌入式半导体合金

    公开(公告)号：US08460980B2

    公开(公告)日：2013-06-11

    申请号：US12709966

    申请日：2010-02-22

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    IPC分类号： H01L27/12 ,  H01L27/762

    CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78654

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.

    摘要翻译： 应变诱导半导体合金可以基于可以深深延伸到栅电极结构下方的空穴形成，这可以通过使用两个蚀刻工艺的顺序来实现。 在第一蚀刻工艺中，可以基于良好限定的横向偏移来形成空腔，以确保栅电极结构的完整性，并且在随后的蚀刻工艺中，空腔可以在横向方向上增加，同时可靠地保持 通道区域的一部分。 因此，可以通过将应变诱导材料适当地定位在通道区域正下方而不损害栅电极结构的完整性来增加应变诱导效率。

    TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE
    7.
    发明申请
    TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE 有权
    包含嵌入式半导体合金的晶体管在栅极电极延伸的漏极和源极区域

    公开(公告)号：US20100219474A1

    公开(公告)日：2010-09-02

    申请号：US12709966

    申请日：2010-02-22

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78654

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.

    摘要翻译： 应变诱导半导体合金可以基于可以深深延伸到栅电极结构下方的空穴形成，这可以通过使用两个蚀刻工艺的顺序来实现。 在第一蚀刻工艺中，可以基于良好限定的横向偏移来形成空腔，以确保栅电极结构的完整性，并且在随后的蚀刻工艺中，空腔可以在横向方向上增加，同时可靠地保持 通道区域的一部分。 因此，可以通过将应变诱导材料适当地定位在通道区域正下方而不损害栅电极结构的完整性来增加应变诱导效率。

    Fabrication of a semiconductor device with extended epitaxial semiconductor regions
    9.
    发明授权
    Fabrication of a semiconductor device with extended epitaxial semiconductor regions 有权
    具有扩展外延半导体区域的半导体器件的制造

    公开(公告)号：US08642420B2

    公开(公告)日：2014-02-04

    申请号：US13219331

    申请日：2011-08-26

    申请人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

    发明人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.

    摘要翻译： 制造半导体器件结构的方法开始于形成覆盖具有第一氮化硅帽的第一栅极结构的氧化物层，并且覆盖具有第二氮化硅帽的第二栅极结构。 第一栅极结构对应于要制造的p型晶体管，并且第二栅极结构对应于待制造的n型晶体管。 该方法通过执行倾斜离子注入程序来将杂质物质的离子注入到第一栅极结构下面的半导体材料的沟道区域中，在此期间离子注入掩模保护第二栅极结构。 此后，去除离子注入掩模和氧化物层，并且对应于第一栅极结构的源区和漏区形成外延半导体材料的区域。 此后，去除第一氮化硅盖和第二氮化硅盖。