-
1.发明授权Fabrication of a semiconductor device with extended epitaxial semiconductor regions 有权具有扩展外延半导体区域的半导体器件的制造公开(公告)号：US08642420B2
公开(公告)日：2014-02-04
申请号：US13219331
申请日：2011-08-26
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.
摘要翻译： 制造半导体器件结构的方法开始于形成覆盖具有第一氮化硅帽的第一栅极结构的氧化物层，并且覆盖具有第二氮化硅帽的第二栅极结构。 第一栅极结构对应于要制造的p型晶体管，并且第二栅极结构对应于待制造的n型晶体管。 该方法通过执行倾斜离子注入程序来将杂质物质的离子注入到第一栅极结构下面的半导体材料的沟道区域中，在此期间离子注入掩模保护第二栅极结构。 此后，去除离子注入掩模和氧化物层，并且对应于第一栅极结构的源区和漏区形成外延半导体材料的区域。 此后，去除第一氮化硅盖和第二氮化硅盖。
-
2.发明申请FABRICATION OF A SEMICONDUCTOR DEVICE WITH EXTENDED EPITAXIAL SEMICONDUCTOR REGIONS 有权具有扩展的外延半导体区域的半导体器件的制造公开(公告)号：US20130052779A1
公开(公告)日：2013-02-28
申请号：US13219331
申请日：2011-08-26
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.
摘要翻译： 制造半导体器件结构的方法开始于形成覆盖具有第一氮化硅帽的第一栅极结构的氧化物层，并且覆盖具有第二氮化硅帽的第二栅极结构。 第一栅极结构对应于要制造的p型晶体管，并且第二栅极结构对应于待制造的n型晶体管。 该方法通过执行倾斜离子注入程序来将杂质物质的离子注入到第一栅极结构下面的半导体材料的沟道区域中，在此期间离子注入掩模保护第二栅极结构。 此后，去除离子注入掩模和氧化物层，并且对应于第一栅极结构的源区和漏区形成外延半导体材料的区域。 此后，去除第一氮化硅盖和第二氮化硅盖。
-
3.发明授权Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same 有权形成具有凹陷源/设计区域的半导体器件的方法以及包括其的半导体器件公开(公告)号：US08476131B2
公开(公告)日：2013-07-02
申请号：US13216791
申请日：2011-08-24
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。
-
4.发明授权Methods for the fabrication of integrated circuits including back-etching of raised conductive structures 有权用于制造包括凸起导电结构的背蚀刻的集成电路的方法公开(公告)号：US08524566B2
公开(公告)日：2013-09-03
申请号：US13331951
申请日：2011-12-20
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823425
摘要： Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.
摘要翻译： 提供了一种用于制造集成电路的方法的实施例。 在一个实施例中，该方法包括产生部分完成的半导体器件，其包括衬底，源极/漏极（S / D）区域，S / D区域之间的沟道区域和沟道区域上的栅极堆叠。 在至少一个S / D区域上形成至少一个凸起的导电结构，并且通过横向间隙与栅极堆叠分离。 然后，升高的导电结构被反蚀刻以增加横向间隙的宽度，并且在完成的半导体器件的操作期间减小凸起的导电结构和栅极堆叠之间的寄生边缘电容。
-
公开(公告)号：US20130183817A1
公开(公告)日：2013-07-18
申请号：US13350891
申请日：2012-01-16
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/2686 , H01L21/28176 , H01L21/31155 , H01L29/512 , H01L29/66545
摘要： Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
摘要翻译： 这里公开了减少诸如晶体管的半导体器件中的栅极泄漏的各种方法。 在一个示例中，本文公开的方法包括执行蚀刻工艺以限定晶体管的栅极绝缘层，其中栅极绝缘层具有蚀刻边缘，执行成角度的离子注入工艺以将离子注入靠近蚀刻的栅极绝缘层 并且在进行成角度的离子注入工艺之后进行退火处理。
-
6.发明申请Methods of Forming Device Level Conductive Contacts to Improve Device Performance and Semiconductor Devices Comprising Such Contacts 审中-公开形成器件级导电触点以提高器件性能的方法和包括这种触点的半导体器件公开(公告)号：US20130207275A1
公开(公告)日：2013-08-15
申请号：US13397199
申请日：2012-02-15
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/1306 , H01L2924/00 , H01L2924/13091
摘要： Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact.
摘要翻译： 本文公开了形成器件级导电触点以改善器件性能的各种方法以及具有这种改进的触发电平触点配置的各种半导体器件。 在一个示例中，本文公开的装置包括定位在第一绝缘材料层中的第一器件级导电触点，其中第一器件级导电触点导电耦合到半导体器件，第二器件级导电触点位于上方并导电耦合 到所述第一器件级触点，其中所述第二器件级触点定位在第二绝缘材料层中，以及用于所述器件的第一布线层，所述第一布线层位于所述第二器件级导电触点的上方并与其导电耦合。
-
公开(公告)号：US08669170B2
公开(公告)日：2014-03-11
申请号：US13350891
申请日：2012-01-16
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/2686 , H01L21/28176 , H01L21/31155 , H01L29/512 , H01L29/66545
摘要： Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
摘要翻译： 这里公开了减少诸如晶体管的半导体器件中的栅极泄漏的各种方法。 在一个示例中，本文公开的方法包括执行蚀刻工艺以限定晶体管的栅极绝缘层，其中栅极绝缘层具有蚀刻边缘，执行成角度的离子注入工艺以将离子注入靠近蚀刻的栅极绝缘层 并且在进行成角度的离子注入工艺之后进行退火处理。
-
8.发明申请Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers 有权用嵌入式半导体材料形成半导体器件作为源/漏区域的方法使用减少的间隔数公开(公告)号：US20130302956A1
公开(公告)日：2013-11-14
申请号：US13470454
申请日：2012-05-14
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.
摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在半导体衬底上形成用于第一晶体管和第二晶体管的栅极结构，在栅极结构上方形成衬底层，并通过衬底层执行多个延伸离子注入工艺 以在第一晶体管和第二晶体管的衬底中形成延伸注入区。 该方法还包括形成靠近第一晶体管的栅极结构的第一侧壁隔离物和位于第二晶体管上方的图案化硬掩模层，执行至少一个蚀刻工艺以去除第一侧壁间隔物，图案化硬掩模层和衬垫 形成靠近两个栅极结构的第二侧壁间隔件，并且执行多个源极/漏极离子注入工艺以在用于第一晶体管和第二晶体管的衬底中形成深源极/漏极注入区域。
-
9.发明申请Methods of Forming a Semiconductor Device with Recessed Source/Drain Regions, and a Semiconductor Device Comprising Same 有权形成具有嵌入式源极/漏极区域的半导体器件的方法以及包括其的半导体器件公开(公告)号：US20130049126A1
公开(公告)日：2013-02-28
申请号：US13216791
申请日：2011-08-24
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。
-
10.发明授权Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers 有权使用减少数量的间隔物形成具有嵌入式半导体材料的半导体器件作为源极/漏极区域的方法公开(公告)号：US09093554B2
公开(公告)日：2015-07-28
申请号：US13470454
申请日：2012-05-14
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.
摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在半导体衬底上形成用于第一晶体管和第二晶体管的栅极结构，在栅极结构上方形成衬底层，并通过衬里层执行多个延伸离子注入工艺 以在第一晶体管和第二晶体管的衬底中形成延伸注入区。 该方法还包括形成靠近第一晶体管的栅极结构的第一侧壁隔离物和位于第二晶体管上方的图案化硬掩模层，执行至少一个蚀刻工艺以去除第一侧壁间隔物，图案化硬掩模层和衬垫 形成靠近两个栅极结构的第二侧壁间隔件，并且执行多个源极/漏极离子注入工艺以在用于第一晶体管和第二晶体管的衬底中形成深源极/漏极注入区域。
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.023 秒)
