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    Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure
    3.
    发明授权
    Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure 有权
    形成半导体结构的方法，包括形成至少一个侧壁间隔结构

    公开(公告)号：US08003460B2

    公开(公告)日：2011-08-23

    申请号：US12028895

    申请日：2008-02-11

    申请人： Frank Wirbeleit ,  Rolf Stephan ,  Peter Javorka

    发明人： Frank Wirbeleit ,  Rolf Stephan ,  Peter Javorka

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823864 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

    摘要： According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process.

    摘要翻译： 根据说明性示例，形成半导体结构的方法包括提供包括第一特征和第二特征的半导体衬底。 在第一特征和第二特征上形成材料层。 在第一特征上形成掩模。 执行适于从材料层的一部分形成邻近第二特征的侧壁间隔结构的至少一个蚀刻工艺。 所述掩模保护所述第一特征上的所述材料层的一部分不受所述至少一个蚀刻工艺的影响。 进行离子注入工艺。 在离子注入过程中，掩模保留在第一个特征之上。

    Self-biasing transistor structure and an SRAM cell having less than six transistors
    7.
    发明申请
    Self-biasing transistor structure and an SRAM cell having less than six transistors 有权
    自偏压晶体管结构和具有小于六个晶体管的SRAM单元

    公开(公告)号：US20060022282A1

    公开(公告)日：2006-02-02

    申请号：US11045177

    申请日：2005-01-28

    申请人： Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

    发明人： Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/105 ,  G11C11/412 ,  H01L27/11 ,  H01L29/7838

    摘要： By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

    摘要翻译： 通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元。 在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元，并且在优选实施例中，具有少至两个单独的晶体管 元素。

    TRANSISTOR WITH STRESS ENHANCED CHANNEL AND METHODS FOR FABRICATION
    8.
    发明申请
    TRANSISTOR WITH STRESS ENHANCED CHANNEL AND METHODS FOR FABRICATION 审中-公开
    具有应力增强通道的晶体管和制造方法

    公开(公告)号：US20130175610A1

    公开(公告)日：2013-07-11

    申请号：US13347435

    申请日：2012-01-10

    申请人： Stefan Flachowsky ,  Frank Wirbeleit

    发明人： Stefan Flachowsky ,  Frank Wirbeleit

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/6653 ,  H01L21/30617 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A transistor device and methods for its fabrication are provided. In an embodiment, the transistor is fabricated within and on a surface of a semiconductor substrate. The method includes forming a gate structure with a dummy gate electrode material overlying the semiconductor substrate. Recesses are etched into the semiconductor substrate adjacent the gate structure to define a narrow region between the recesses at a selected depth under the surface. The recesses are filled with a stress-inducing material and the dummy gate electrode material is removed to expose the semiconductor substrate. The method further provides for etching the exposed semiconductor substrate to form a recessed gate surface and defining a channel under the recessed gate surface in the narrow region.

    摘要翻译： 提供了晶体管器件及其制造方法。 在一个实施例中，晶体管制造在半导体衬底的内表面上。 该方法包括形成具有覆盖在半导体衬底上的虚拟栅极电极材料的栅极结构。 凹槽被蚀刻到与栅极结构相邻的半导体衬底中，以在表面下方的选定深度处限定凹陷之间的窄区域。 这些凹部填充有应力诱导材料，并且去除伪栅电极材料以暴露半导体衬底。 该方法还提供了蚀刻暴露的半导体衬底以形成凹入的栅极表面并且在狭窄区域中限定凹陷栅极表面下方的沟道。

    Three-dimensional transistor with double channel configuration
    9.
    发明授权
    Three-dimensional transistor with double channel configuration 有权
    具有双通道配置的三维晶体管

    公开(公告)号：US08164145B2

    公开(公告)日：2012-04-24

    申请号：US12425462

    申请日：2009-04-17

    申请人： Frank Wirbeleit

    发明人： Frank Wirbeleit

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/42392 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

    摘要： A three-dimensional double channel transistor configuration is provided in which a second channel region may be embedded into the body region of the transistor, thereby providing a three-state behavior, which may therefore increase functionality of conventional three-dimensional transistor architectures. The double channel three-dimensional transistors may be used for forming a static RAM cell with a reduced number of transistors, while also providing scalability by taking advantage of the enhanced controllability of FinFETS and nano pipe transistor architectures.

    摘要翻译： 提供三维双通道晶体管配置，其中第二沟道区可嵌入晶体管的体区，从而提供三态行为，因此可增加常规三维晶体管架构的功能。 双通道三维晶体管可以用于形成具有减少数量的晶体管的静态RAM单元，同时还通过利用FinFETS和纳米管晶体管架构的增强的可控性来提供可扩展性。

    Body controlled double channel transistor and circuits comprising the same
    10.
    发明授权
    Body controlled double channel transistor and circuits comprising the same 有权
    体控双通道晶体管和包括其的电路

    公开(公告)号：US07880239B2

    公开(公告)日：2011-02-01

    申请号：US12144281

    申请日：2008-06-23

    申请人： Frank Wirbeleit

    发明人： Frank Wirbeleit

    IPC分类号： H01L29/78 ,  H01L27/11

    CPC分类号： H01L27/11 ,  H01L29/7841

    摘要： By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell, which may result in increased information density.

    摘要翻译： 通过提供体控双通道晶体管，可以实现与增强的稳定性相结合的增加的功能。 例如，可以基于体控双通道晶体管形成可用于静态RAM单元的触发器电路，从而减少每个单元所需的晶体管数量，这可能导致信息密度增加。