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    Fabrication of a semiconductor device with extended epitaxial semiconductor regions
    2.
    发明授权
    Fabrication of a semiconductor device with extended epitaxial semiconductor regions 有权
    具有扩展外延半导体区域的半导体器件的制造

    公开(公告)号：US08642420B2

    公开(公告)日：2014-02-04

    申请号：US13219331

    申请日：2011-08-26

    申请人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

    发明人： Stefan Flachowsky ,  Frank Wirbeleit ,  Matthias Kessler ,  Ricardo P. Mikalo

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.

    摘要翻译： 制造半导体器件结构的方法开始于形成覆盖具有第一氮化硅帽的第一栅极结构的氧化物层，并且覆盖具有第二氮化硅帽的第二栅极结构。 第一栅极结构对应于要制造的p型晶体管，并且第二栅极结构对应于待制造的n型晶体管。 该方法通过执行倾斜离子注入程序来将杂质物质的离子注入到第一栅极结构下面的半导体材料的沟道区域中，在此期间离子注入掩模保护第二栅极结构。 此后，去除离子注入掩模和氧化物层，并且对应于第一栅极结构的源区和漏区形成外延半导体材料的区域。 此后，去除第一氮化硅盖和第二氮化硅盖。

    Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode
    4.
    发明授权
    Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode 有权
    晶体管包括在栅极电极下方延伸的漏极和源极区域中的嵌入式半导体合金

    公开(公告)号：US08460980B2

    公开(公告)日：2013-06-11

    申请号：US12709966

    申请日：2010-02-22

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    IPC分类号： H01L27/12 ,  H01L27/762

    CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78654

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.

    摘要翻译： 应变诱导半导体合金可以基于可以深深延伸到栅电极结构下方的空穴形成，这可以通过使用两个蚀刻工艺的顺序来实现。 在第一蚀刻工艺中，可以基于良好限定的横向偏移来形成空腔，以确保栅电极结构的完整性，并且在随后的蚀刻工艺中，空腔可以在横向方向上增加，同时可靠地保持 通道区域的一部分。 因此，可以通过将应变诱导材料适当地定位在通道区域正下方而不损害栅电极结构的完整性来增加应变诱导效率。

    TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS
    5.
    发明申请
    TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS 有权
    带引导形状源/漏区的晶体管

    公开(公告)号：US20130032864A1

    公开(公告)日：2013-02-07

    申请号：US13204271

    申请日：2011-08-05

    申请人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

    发明人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/6653 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers.

    摘要翻译： 器件形成有通过各向同性蚀刻然后进行各向异性蚀刻形成的引线形状的源极/漏极区域。 实施例包括在衬底上形成栅极，在栅极的每一侧上形成第一间隔物，在栅极的每一侧上在衬底中形成源极/漏极区域，其中每个源极/漏极区域在第一间隔物之下延伸，但是 由基板的一部分与之隔开，并具有基本上水平的底面。 实施例还包括通过将空腔形成为与第一间隔件相邻的第一深度并形成第二腔至第一腔的第二深度并且在第一间隔物下方横向延伸来形成每个源/漏区。

    Ionization Method, Ion Producing Device and Uses of the Same in Ion Mobility Spectrometry
    7.
    发明申请
    Ionization Method, Ion Producing Device and Uses of the Same in Ion Mobility Spectrometry 有权
    电离法，离子生成装置及其在离子流动性光谱法中的应用

    公开(公告)号：US20120235032A1

    公开(公告)日：2012-09-20

    申请号：US13499506

    申请日：2010-08-26

    申请人： Johann Goebel ,  Andreas Langmeier ,  Matthias Kessler

    发明人： Johann Goebel ,  Andreas Langmeier ,  Matthias Kessler

    IPC分类号： H01J49/26 ,  H01J27/24 ,  H01J27/02

    CPC分类号： H01J49/0027 ,  G01N27/64 ,  H01J49/0031 ,  H01J49/162

    摘要： A method for ionizing, using pulses of ionization radiation, an analyte to be examined by way of ion mobility spectrometry using a pulse sequence is modulated with a known time-variable impression pattern is provided. An ionization device for carrying out the method and an ion mobility spectrometry method and an ion mobility spectrometry device that use the ionization method and/or the ionization device are also provided.

    摘要翻译： 提供了使用脉冲序列离子化电离辐射待测分析物的方法，该分析物通过离子迁移光谱法被调制，并且已知的时间变化的印模模式被调制。 还提供了用于实施该方法的离子化装置和使用该离子化方法和/或电离装置的离子迁移谱分析方法和离子迁移率光谱测定装置。

    Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing heat generation
    9.
    发明授权
    Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing heat generation 有权
    半导体器件包括通过增强发热而提高编程效率的基于金属的eFuse

    公开(公告)号：US09287211B2

    公开(公告)日：2016-03-15

    申请号：US13032710

    申请日：2011-02-23

    申请人： Andreas Kurz ,  Jens Poppe ,  Matthias Kessler

    发明人： Andreas Kurz ,  Jens Poppe ,  Matthias Kessler

    IPC分类号： H01L23/535 ,  H01L29/00 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.

    摘要翻译： 在复杂的半导体器件中，可以在金属化系统中提供电子熔丝，其中金属线的优越的二维结构，例如螺旋状结构，可以在中心线部分提供优异的热条件，反过来 可能导致给定编程电流更显着的电迁移效应。 因此，至少在一个横向方向上的电子熔断器的尺寸以及连接到电子熔断器的相应的晶体管的宽度可以减小。