公开(公告)号：US07034610B2

公开(公告)日：2006-04-25

申请号：US10861379

申请日：2004-06-07

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US08334721B2

公开(公告)日：2012-12-18

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US06747510B2

公开(公告)日：2004-06-08

申请号：US10163143

申请日：2002-06-07

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F152

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US20120086592A1

公开(公告)日：2012-04-12

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Anges N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Anges N. Woo

IPC分类号： H03M1/66

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US06727729B2

公开(公告)日：2004-04-27

申请号：US09949662

申请日：2001-09-12

申请人： Todd L. Brooks ,  Anilkumar V. Tammineedi

发明人： Todd L. Brooks ,  Anilkumar V. Tammineedi

IPC分类号： H03K190175

CPC分类号： H03F1/3205 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/168 ,  H03F2200/331 ,  H03F2200/417 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/5031

摘要： A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

摘要翻译： 基于源极跟随器晶体管的缓冲器提供高线性度。 复制晶体管用于产生基本上等于缓冲器的输出电压的复制电压。 复制电压由电平移位电路电平移位并施加在源极跟随器晶体管的漏极处，以提高缓冲器的线性。 缓冲器可以与开关电容器采样电路结合使用。 可以使用阻尼电路来减少由于取样引起的充电毛刺。 阻尼电路可以是低通滤波器。 缓冲器可以用在从输入信号产生输出信号并控制输出信号电平的接口电路中。

公开(公告)号：US07049848B2

公开(公告)日：2006-05-23

申请号：US10626701

申请日：2003-07-25

申请人： Todd L. Brooks ,  Anilkumar V. Tammineedi

发明人： Todd L. Brooks ,  Anilkumar V. Tammineedi

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03F1/3205 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/168 ,  H03F2200/331 ,  H03F2200/417 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/5031

摘要： A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

公开(公告)号：US07126377B2

公开(公告)日：2006-10-24

申请号：US11355174

申请日：2006-02-16

申请人： Todd L. Brooks ,  Anilkumar V. Tammineedi

发明人： Todd L. Brooks ,  Anilkumar V. Tammineedi

IPC分类号： H03K19/0175

CPC分类号： H03F1/3205 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/168 ,  H03F2200/331 ,  H03F2200/417 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/5031

摘要： A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.