摘要:
A clamp circuit for a read-only-memory (ROM) device provides clamp voltages which can uniformly compensate for the parasitic capacitance on ROM word lines and improve the performance of the ROM device. The clamp circuit includes an active load, a plurality of amplifiers and a transmission gate. The amplifiers have various trip voltages and are controlled by different decoding signals for providing various clamp voltages to different word lines in the ROM device. Each amplifier is composed of a NOR gate and a transistor. The amplifier trip voltages can be easily set to desired values when designing NOR gate layout patterns without additional complicated processes being introduced into the fabrication methodology of a semiconductor integrated circuit.
摘要:
A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.
摘要:
A ROM array with coding after metallization comprises a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, a plurality of word lines, a plurality of first control lines, a plurality of second control lines and a plurality of selecting lines. Memory cells of the ROM array are formed by the intersection of the word lines and the first and second bit lines, wherein the word lines are polysilicon gates and the bit lines are drain/source diffusion regions. The third bit lines are metal lines above the first bit lines. The third bit lines are not wide enough to cover spacings between the first and second bit lines, thus exposing spaces for code implantation. The first and second control lines intersect the first and second bit lines to form a number of switches for controlling data reading paths to The memory cells. The positions and ON/OFF states of the switches are designed to provide at least two data reading paths to each memory cell. Thus, the sensing currents in the bit lines are increased and become more uniform.
摘要:
A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.
摘要:
A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.
摘要:
A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.
摘要:
A touch-sensitive liquid crystal display (LCD) device includes a first substrate, a second substrate generally opposite to the first substrate, a liquid crystal layer sandwiched between the first substrate and the second substrate, a first scan line, a data line perpendicular to the first scan line, a sensing line parallel to the data line, and a first transistor formed at an inner side of the first substrate adjacent to the liquid crystal layer, and a common electrode formed at an inner side of the second substrate adjacent to the liquid crystal layer. A gate of the first transistor is electrically connected to the first gate line. A drain of the first transistor is electrically connected to sensing line. A source of the first transistor is electrically connectable to the common electrode depending on an external pressure applied on the second substrate.
摘要:
A touching display panel and a display device using the same are provided. The touching display panel includes a liquid crystal layer, a first substrate having a hard surface structure, a second substrate, a touch sensor layer, a thin-film transistor layer, and a color filter layer. The first and second substrates are respectively disposed at two sides of the liquid crystal layer. The touch sensor layer is disposed between the first substrate and the liquid crystal layer, and is formed on the first substrate. The thin-film transistor layer and the color filter layer are both disposed between the first substrate and the second substrate. At least one of the thin-film transistor layer and the color filter layer is formed on the first substrate.
摘要:
A in-cell touch-sensitive liquid crystal display device (LCD) includes a first substrate, a second substrate opposite to the first substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a first sensing line and a second sensing line disposed on the second substrate, a first conductive layer and a second conductive layer electrically connected to the first sensing line and the second sensing line, respectively, and electrically isolated from each other by a gap existing therebetween. The in-cell touch-sensitive LCD device further includes a spacer disposed on the first substrate and corresponding to the gap. The spacer is electrically connected to the first conductive layer and the second conductive layer in response to an external pressure.
摘要:
An exemplary interconnected structure for transferring a voltage signal to a thin film transistor (TFT) array substrate includes a first metal layer (310), a second metal layer (320) isolated from the first metal layer and a conductive layer (340) isolated from the second metal layer. The first metal layer is electrically connected to the conductive layer via at least one first contact hole (351, 352) thereby obtaining a first contacting area between the first metal layer and the conductive layer. The second metal layer is electrically connected to the conductive layer via at least one second contact hole (353, 354) thereby obtaining a second contacting area between the second metal layer and the conductive layer. A radio of the sum of the first contacting area and the second contacting area to the voltage value of the voltage signal is equal to or greater than 0.233 μm2/mv.