Clamp circuit for read-only-memory devices
    1.
    发明授权
    Clamp circuit for read-only-memory devices 失效
    只读存储器件的钳位电路

    公开(公告)号:US5612915A

    公开(公告)日:1997-03-18

    申请号:US591390

    申请日:1996-01-25

    IPC分类号: G11C7/12 G11C11/34

    CPC分类号: G11C7/12

    摘要: A clamp circuit for a read-only-memory (ROM) device provides clamp voltages which can uniformly compensate for the parasitic capacitance on ROM word lines and improve the performance of the ROM device. The clamp circuit includes an active load, a plurality of amplifiers and a transmission gate. The amplifiers have various trip voltages and are controlled by different decoding signals for providing various clamp voltages to different word lines in the ROM device. Each amplifier is composed of a NOR gate and a transistor. The amplifier trip voltages can be easily set to desired values when designing NOR gate layout patterns without additional complicated processes being introduced into the fabrication methodology of a semiconductor integrated circuit.

    摘要翻译: 用于只读存储器(ROM)器件的钳位电路提供钳位电压,其可以均匀地补偿ROM字线上的寄生电容并且提高ROM器件的性能。 钳位电路包括有源负载,多个放大器和传输门。 放大器具有各种跳闸电压,并且由不同的解码信号控制,以向ROM器件中的不同字线提供各种钳位电压。 每个放大器由或非门和晶体管组成。 当设计NOR门布局图案时,放大器跳闸电压可以很容易地设置为所需的值,而不会在半导体集成电路的制造方法中引入额外的复杂工艺。

    PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME 有权
    照片检测器及其制造方法

    公开(公告)号:US20110316830A1

    公开(公告)日:2011-12-29

    申请号:US13227455

    申请日:2011-09-07

    IPC分类号: G09G5/10 H01L31/12 H01L31/18

    摘要: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

    摘要翻译: 公开了一种光电检测器。 光检测器包括衬底,第一图案化半导体层,电介质层,图案化导电层,层间电介质,第二图案化半导体层,设置在层间电介质上的两个第一电极和设置在层间电介质上的两个第二电极 第二半导体层的部分。 具有第一掺杂区域和第二掺杂区域的第一图案化半导体层设置在晶体管区域上。 介电层设置成覆盖基板和第一半导体层,图案化的导电层设置在电介质层上,并且具有适于暴露第一掺杂区域和第二掺杂区域的至少两个开口的层间电介质是 被设置成覆盖电介质层。 第二图案化半导体层设置在光敏区域上,并且第一电极电连接到第一图案化半导体层。

    Read-only-memory array with coding after metallization
    3.
    发明授权
    Read-only-memory array with coding after metallization 失效
    只读存储器阵列,具有金属化后的编码

    公开(公告)号:US5561624A

    公开(公告)日:1996-10-01

    申请号:US495761

    申请日:1995-06-26

    CPC分类号: G11C17/126 H01L27/112

    摘要: A ROM array with coding after metallization comprises a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, a plurality of word lines, a plurality of first control lines, a plurality of second control lines and a plurality of selecting lines. Memory cells of the ROM array are formed by the intersection of the word lines and the first and second bit lines, wherein the word lines are polysilicon gates and the bit lines are drain/source diffusion regions. The third bit lines are metal lines above the first bit lines. The third bit lines are not wide enough to cover spacings between the first and second bit lines, thus exposing spaces for code implantation. The first and second control lines intersect the first and second bit lines to form a number of switches for controlling data reading paths to The memory cells. The positions and ON/OFF states of the switches are designed to provide at least two data reading paths to each memory cell. Thus, the sensing currents in the bit lines are increased and become more uniform.

    摘要翻译: 在金属化之后编码的ROM阵列包括多个第一位线,多个第二位线,多个第三位线,多个字线,多个第一控制线,多个第二控制线和 多条选线。 ROM阵列的存储单元由字线和第一和第二位线的交点形成,其中字线是多晶硅栅极,位线是漏极/源极扩散区域。 第三位线是位于第一位线之上的金属线。 第三位线的宽度不足以覆盖第一和第二位线之间的间隔,从而暴露用于代码注入的空间。 第一和第二控制线与第一和第二位线相交以形成用于控制到存储单元的数据读取路径的多个开关。 开关的位置和开/关状态被设计为向每个存储单元提供至少两条数据读取路径。 因此,位线中的感测电流增加并变得更均匀。

    PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME
    4.
    发明申请
    PHOTO DETECTOR AND METHOD FOR FABRICATING THE SAME 有权
    照片检测器及其制造方法

    公开(公告)号:US20090027371A1

    公开(公告)日:2009-01-29

    申请号:US11943602

    申请日:2007-11-21

    IPC分类号: G09G3/00 H01L31/18 H01L31/062

    摘要: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

    摘要翻译: 公开了一种光电检测器。 光检测器包括基板,具有第一状态的第一图案化半导体层,电介质层,图案化导电层,层间电介质,具有第二状态的第二图案化半导体层,设置在第二状态的第二图案化半导体层, 层电介质和设置在第二半导体层的部分上的两个第二电极。 具有第一掺杂区域和第二掺杂区域的第一图案化半导体层设置在衬底的晶体管区域上。 介电层设置成覆盖基板和第一半导体层,图案化的导电层设置在电介质层上,并且具有适于暴露第一掺杂区和第二掺杂区的至少两个开口的层间电介质是 被设置成覆盖电介质层。 第二图案化半导体层设置在光敏区域上,并且第一电极电连接到第一图案化半导体层。

    Display panel
    5.
    发明授权
    Display panel 有权
    显示面板

    公开(公告)号:US08599181B2

    公开(公告)日:2013-12-03

    申请号:US13227455

    申请日:2011-09-07

    IPC分类号: G06F3/038

    摘要: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

    摘要翻译: 公开了一种光电检测器。 光检测器包括衬底,第一图案化半导体层,电介质层,图案化导电层,层间电介质,第二图案化半导体层,设置在层间电介质上的两个第一电极和设置在层间电介质上的两个第二电极 第二半导体层的部分。 具有第一掺杂区域和第二掺杂区域的第一图案化半导体层设置在晶体管区域上。 介电层设置成覆盖基板和第一半导体层,图案化的导电层设置在电介质层上,并且具有适于暴露第一掺杂区域和第二掺杂区域的至少两个开口的层间电介质是 被设置成覆盖电介质层。 第二图案化半导体层设置在光敏区域上,并且第一电极电连接到第一图案化半导体层。

    Photo detector and method for fabricating the same
    6.
    发明授权
    Photo detector and method for fabricating the same 有权
    光电检测器及其制造方法

    公开(公告)号:US08054304B2

    公开(公告)日:2011-11-08

    申请号:US11943602

    申请日:2007-11-21

    IPC分类号: G06F3/038 G09G5/00

    摘要: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

    摘要翻译: 公开了一种光电检测器。 光检测器包括基板,具有第一状态的第一图案化半导体层,电介质层,图案化导电层,层间电介质,具有第二状态的第二图案化半导体层,设置在第二状态的第二图案化半导体层, 层电介质和设置在第二半导体层的部分上的两个第二电极。 具有第一掺杂区域和第二掺杂区域的第一图案化半导体层设置在衬底的晶体管区域上。 介电层设置成覆盖基板和第一半导体层,图案化的导电层设置在电介质层上,并且具有适于暴露第一掺杂区和第二掺杂区的至少两个开口的层间电介质是 被设置成覆盖电介质层。 第二图案化半导体层设置在光敏区域上,并且第一电极电连接到第一图案化半导体层。

    Touch-sensitive liquid crystal display device with built-in touch mechanism and
method and method for driving same
    7.
    发明申请
    Touch-sensitive liquid crystal display device with built-in touch mechanism and method and method for driving same 审中-公开
    触摸式液晶显示装置,内置触摸机构和

    公开(公告)号:US20090289912A1

    公开(公告)日:2009-11-26

    申请号:US12454873

    申请日:2009-05-26

    IPC分类号: G06F3/041

    CPC分类号: G06F3/0412

    摘要: A touch-sensitive liquid crystal display (LCD) device includes a first substrate, a second substrate generally opposite to the first substrate, a liquid crystal layer sandwiched between the first substrate and the second substrate, a first scan line, a data line perpendicular to the first scan line, a sensing line parallel to the data line, and a first transistor formed at an inner side of the first substrate adjacent to the liquid crystal layer, and a common electrode formed at an inner side of the second substrate adjacent to the liquid crystal layer. A gate of the first transistor is electrically connected to the first gate line. A drain of the first transistor is electrically connected to sensing line. A source of the first transistor is electrically connectable to the common electrode depending on an external pressure applied on the second substrate.

    摘要翻译: 触摸式液晶显示器(LCD)装置包括第一基板,与第一基板大致相对的第二基板,夹在第一基板和第二基板之间的液晶层,第一扫描线,与 第一扫描线,与数据线平行的检测线,以及形成在与液晶层相邻的第一基板的内侧的第一晶体管,以及形成在与第二基板相邻的第二基板的内侧的公共电极 液晶层。 第一晶体管的栅极电连接到第一栅极线。 第一晶体管的漏极电连接到感测线。 第一晶体管的源极可以根据施加在第二衬底上的外部压力而电连接到公共电极。

    Touch-sensitive liquid crystal display device
    9.
    发明授权
    Touch-sensitive liquid crystal display device 有权
    触摸式液晶显示装置

    公开(公告)号:US08279361B2

    公开(公告)日:2012-10-02

    申请号:US12844803

    申请日:2010-07-27

    IPC分类号: G02F1/1335

    摘要: A in-cell touch-sensitive liquid crystal display device (LCD) includes a first substrate, a second substrate opposite to the first substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a first sensing line and a second sensing line disposed on the second substrate, a first conductive layer and a second conductive layer electrically connected to the first sensing line and the second sensing line, respectively, and electrically isolated from each other by a gap existing therebetween. The in-cell touch-sensitive LCD device further includes a spacer disposed on the first substrate and corresponding to the gap. The spacer is electrically connected to the first conductive layer and the second conductive layer in response to an external pressure.

    摘要翻译: 单元内触摸式液晶显示装置(LCD)包括第一基板,与第一基板相对的第二基板,设置在第一基板和第二基板之间的液晶层,第一感测线和第二感测 设置在第二基板上的第一导电层和第二导电层,第一导电层和第二导电层分别电连接到第一感测线和第二感测线,并且通过它们之间的间隙彼此电隔离。 单元内触敏LCD装置还包括设置在第一基板上并对应于间隙的间隔件。 间隔物响应于外部压力而电连接到第一导电层和第二导电层。

    Interconnected structure for TFT-array substrate
    10.
    发明申请
    Interconnected structure for TFT-array substrate 审中-公开
    TFT阵列基板互连结构

    公开(公告)号:US20090152730A1

    公开(公告)日:2009-06-18

    申请号:US12316607

    申请日:2008-12-15

    IPC分类号: H01L23/535

    CPC分类号: H01L27/124

    摘要: An exemplary interconnected structure for transferring a voltage signal to a thin film transistor (TFT) array substrate includes a first metal layer (310), a second metal layer (320) isolated from the first metal layer and a conductive layer (340) isolated from the second metal layer. The first metal layer is electrically connected to the conductive layer via at least one first contact hole (351, 352) thereby obtaining a first contacting area between the first metal layer and the conductive layer. The second metal layer is electrically connected to the conductive layer via at least one second contact hole (353, 354) thereby obtaining a second contacting area between the second metal layer and the conductive layer. A radio of the sum of the first contacting area and the second contacting area to the voltage value of the voltage signal is equal to or greater than 0.233 μm2/mv.

    摘要翻译: 用于将电压信号传送到薄膜晶体管(TFT)阵列衬底的示例性互连结构包括第一金属层(310),与第一金属层隔离的第二金属层(320)和与第一金属层隔离的导电层(340) 第二金属层。 第一金属层经由至少一个第一接触孔(351,352)电连接到导电层,从而获得第一金属层和导电层之间的第一接触面积。 第二金属层经由至少一个第二接触孔(353,354)电连接到导电层,从而获得第二金属层和导电层之间的第二接触面积。 第一接触面积和第二接触面积之和的无线电电压与电压信号的电压值等于或大于0.233m2 / mv。