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    SRAM device having forward body bias control
    1.
    发明授权
    SRAM device having forward body bias control 有权
    具有前向偏置控制的SRAM器件

    公开(公告)号：US07423899B2

    公开(公告)日：2008-09-09

    申请号：US10812894

    申请日：2004-03-31

    申请人： Stephen H. Tang ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz

    发明人： Stephen H. Tang ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz

    IPC分类号： G11C11/00 ,  G11C5/14

    CPC分类号： G11C11/412

    摘要： A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.

    摘要翻译： 提供具有多个存储单元的SRAM器件。 每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体，以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。 功率控制单元可以控制每个PMOS晶体管的电源电压，并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。

    Dual gate oxide one time programmable (OTP) antifuse cell
    5.
    发明授权
    Dual gate oxide one time programmable (OTP) antifuse cell 有权
    双栅氧化层一次可编程（OTP）反熔丝

    公开(公告)号：US07280425B2

    公开(公告)日：2007-10-09

    申请号：US11239903

    申请日：2005-09-30

    申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027

    摘要： A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

    摘要翻译： 一次性可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。 存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则在存取晶体管的栅极/漏极结附近的电压不足以引起栅极氧化物 存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

    OTP antifuse cell and cell array
    6.
    发明授权
    OTP antifuse cell and cell array 有权
    OTP反熔丝电池和电池阵列

    公开(公告)号：US07102951B2

    公开(公告)日：2006-09-05

    申请号：US10979605

    申请日：2004-11-01

    申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    IPC分类号： G11C17/18

    CPC分类号： G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027

    摘要： Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

    摘要翻译： 包括一次性可编程反熔丝电池的不同实施例。 在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。 反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。 感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。 高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。

    Memory cell without halo implant
    7.
    发明授权
    Memory cell without halo implant 有权
    无光晕植入的记忆细胞

    公开(公告)号：US07355246B2

    公开(公告)日：2008-04-08

    申请号：US11268430

    申请日：2005-11-07

    申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： H01L29/76

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

    摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

    摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。