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公开(公告)号：US07245548B2
公开(公告)日：2007-07-17
申请号：US10900246
申请日：2004-07-27
申请人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
发明人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。
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公开(公告)号：US06717873B2
公开(公告)日：2004-04-06
申请号：US10317106
申请日：2002-12-12
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C11/4091
摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
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公开(公告)号：US07746720B2
公开(公告)日：2010-06-29
申请号：US11879396
申请日：2007-07-17
申请人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
发明人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。
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4.发明授权Apparatus and method to reduce undesirable effects caused by a fault in a memory device 有权用于减少由存储器件中的故障引起的不期望的影响的装置和方法公开(公告)号：US07336522B2
公开(公告)日：2008-02-26
申请号：US11489119
申请日：2006-07-19
IPC分类号： G11C11/24
CPC分类号： G11C7/12 , G11C7/02 , G11C7/1048 , G11C11/4085 , G11C11/4094 , G11C11/4096 , G11C2207/002
摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
摘要翻译： 提供了一种减少存储器件中的电流的方法和装置。 外围设备控制信号被转换为字线关断电压电平，例如负字线电压。 转换后的信号可防止外围设备在字线关闭模式下传导电流，即使发生字线数字短路。 控制信号可以包括列选择装置的列选择信号和用于感测放大器的有源上拉信号等。 此外，为存储器件提供具有高电阻和低电阻分量的均衡电路。 均衡电路限制电流，即使发生字线数字短路。
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公开(公告)号：US07173855B2
公开(公告)日：2007-02-06
申请号：US10930526
申请日：2004-08-31
申请人： Stephen R. Porter , Scott J. Derner
发明人： Stephen R. Porter , Scott J. Derner
IPC分类号： G11C11/34
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.
摘要翻译： 公开了通过轻度掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得区域的电阻以非线性方式响应于电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。
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公开(公告)号：US07142446B2
公开(公告)日：2006-11-28
申请号：US10902728
申请日：2004-07-29
IPC分类号： G11C11/24
CPC分类号： G11C7/12 , G11C7/02 , G11C7/1048 , G11C11/4085 , G11C11/4094 , G11C11/4096 , G11C2207/002
摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
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公开(公告)号：US07091067B2
公开(公告)日：2006-08-15
申请号：US10930511
申请日：2004-08-31
申请人： Stephen R. Porter , Scott J. Derner
发明人： Stephen R. Porter , Scott J. Derner
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.
摘要翻译： 公开了通过轻度掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得区域的电阻以非线性方式响应于电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。
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公开(公告)号：US06816425B2
公开(公告)日：2004-11-09
申请号：US10775231
申请日：2004-02-11
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C11/4091
摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
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公开(公告)号：US07466618B2
公开(公告)日：2008-12-16
申请号：US10930517
申请日：2004-08-31
申请人： Stephen R. Porter , Scott J. Derner
发明人： Stephen R. Porter , Scott J. Derner
IPC分类号： G11C17/18
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.
摘要翻译： 提供了通过轻掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得该区域的电阻以非线性方式响应电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。
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公开(公告)号：US06859408B2
公开(公告)日：2005-02-22
申请号：US10230637
申请日：2002-08-29
申请人： Stephen R. Porter , Scott J. Derner
发明人： Stephen R. Porter , Scott J. Derner
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.
摘要翻译： 用于通过轻掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得该区域的电阻以非线性方式响应于电压变化。 以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。
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