公开(公告)号：US20050041734A1

公开(公告)日：2005-02-24

申请号：US10501771

申请日：2003-01-21

申请人： Matthew Walker ,  Adrian Thurlow ,  Stephen Webster

发明人： Matthew Walker ,  Adrian Thurlow ,  Stephen Webster

IPC分类号： G06T9/00 ,  G08B13/196 ,  H04N7/18 ,  H04N7/12

CPC分类号： G08B13/19667 ,  G06T9/004 ,  H04N7/18

摘要： A method of generating video data for transmission to a user particularly for use in a video surveillance system. The method comprises generating a first representation of a first image and one or more further representations of the first image are then generated, said further representation(s) being predicted from a previously generated representation of the first image. In response to a request for a subsequent image, a first representation of said subsequent image being predicted from a representation of the first image. Then one or more further representations of said subsequent image are generated, said further representations of said subsequent image being predicted from a previously generated representation of said subsequent image. Thus, the same source data for a first image is fed into the encoder, so producing a progressive still image at the decoder. When a different image is required, the encoder substitutes, as the input to the encoder, the source picture from the requested point in time. This source picture is encoded predictively from the original image

摘要翻译： 一种生成用于传送给用户的视频数据的方法，特别是用于视频监控系统中。 该方法包括生成第一图像的第一表示，然后生成第一图像的一个或多个另外的表示，所述另外的表示从先前生成的第一图像的表示预测。 响应于对后续图像的请求，从第一图像的表示预测所述后续图像的第一表示。 然后产生所述后续图像的一个或多个进一步表示，所述后续图像的所述另外的表示是根据先前生成的所述后续图像的表示进行预测的。 因此，用于第一图像的相同源数据被馈送到编码器中，因此在解码器处产生逐行静态图像。 当需要不同的图像时，编码器将来自所请求的时间点作为编码器的输入替代源图像。 该源图像从原始图像预测编码

公开(公告)号：US5359299A

公开(公告)日：1994-10-25

申请号：US6396

申请日：1993-01-21

申请人： Stephen Webster

发明人： Stephen Webster

IPC分类号： H03L7/093 ,  G05F3/22 ,  H02M3/07 ,  H03L7/089 ,  H03K17/28 ,  H03K17/56

CPC分类号： G05F3/22 ,  H02M3/07 ,  H03L7/0896

摘要： A device for converting binary logic pulses into an output current and the output current being switchable between a positive and negative polarity. The device provides a charge pump circuit which is suitable for the phase-detector stage in a phase-locked loop (PLL) circuit. The charge pump circuit comprises an input stage for the "UP" binary logic pulses and a second stage for the "DOWN" binary logic pulses. The input stages comprise emitted-coupled transistor pairs. The circuit includes current sources and current sinks for generating the output current in the input stages in response to the binary logic pulses. The circuit features a pair of switch diodes coupled between the outputs of the input stages. The diodes form a commutator which controls the direction of the output current and the leakage current during the idle states. The circuit also includes a clamping circuit to limit the voltage swing across the switching diodes. The charge pump circuit according to the present invention exhibits a fast response time, a symmetrical response to the binary logic pulses, and virtually zero leakage current in the idle state. The charge pump circuit utilizes non-complimentary bipolar processes and is suitable for a monolithic integrated circuit implementation.

摘要翻译： 用于将二进制逻辑脉冲转换为输出电流并且输出电流可在正极性和负极性之间切换的装置。 该器件提供了适用于锁相环（PLL）电路中的相位检测器级的电荷泵电路。 电荷泵电路包括用于“UP”二进制逻辑脉冲的输入级和用于“DOWN”二进制逻辑脉冲的第二级。 输入级包括发射耦合晶体管对。 该电路包括用于响应二进制逻辑脉冲在输入级产生输出电流的电流源和电流吸收器。 该电路具有耦合在输入级的输出端之间的一对开关二极管。 二极管形成一个整流子，它在空闲状态下控制输出电流的方向和漏电流。 该电路还包括钳位电路，以限制开关二极管的电压摆幅。 根据本发明的电荷泵电路表现出快速响应时间，对二进制逻辑脉冲的对称响应，以及在空闲状态下几乎为零的泄漏电流。 电荷泵电路采用非互补双极性工艺，适用于单片集成电路实现。

公开(公告)号：US20070242742A1

公开(公告)日：2007-10-18

申请号：US11820311

申请日：2007-06-19

申请人： Aapoolcoyuz Biman ,  John Hudson ,  Eliyahu Zamir ,  Stephen Webster

发明人： Aapoolcoyuz Biman ,  John Hudson ,  Eliyahu Zamir ,  Stephen Webster

IPC分类号： H03K5/159

CPC分类号： G09G5/006 ,  G09G2330/04 ,  G09G2370/047 ,  H03F3/191 ,  H03F3/45197 ,  H03F2203/45458 ,  H03F2203/45496 ,  H03F2203/45612 ,  H03F2203/45702 ,  H04L25/0272 ,  H04L25/03878 ,  H04L25/08 ,  H04L25/10

摘要： A digital communication system for transmitting and receiving video data signals and control data signals over a transmission line comprises an open-loop equalizer circuit and a control data extension circuit. The open-loop equalizer circuit is operable to receive video signals transmitted over the transmission line and output equalized video data signals. The control data extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the control data signal, and clamp the receive end of the transmission line during a negative transition of the control data signal.

摘要翻译： 用于通过传输线发送和接收视频数据信号和控制数据信号的数字通信系统包括开环均衡器电路和控制数据扩展电路。 开环均衡器电路可操作以接收通过传输线传输的视频信号并输出​​均衡的视频数据信号。 控制数据扩展电路可操作以在控制数据信号的正转换期间在传输线的接收端注入升压电流，并且在控制数据信号的负转变期间钳位传输线的接收端。

公开(公告)号：US20060134794A1

公开(公告)日：2006-06-22

申请号：US11273258

申请日：2005-11-14

申请人： Stephen Webster

发明人： Stephen Webster

IPC分类号： G01N33/00

CPC分类号： G01N33/574 ,  G01N33/84 ,  G01N2333/90209

摘要： Silver (II) Oxide preferentially reacts with tNOX a cancer-specific ECTO-NOX protein of the surface of cancer cells. The combination of the cancer specificity of tNOX and the interaction of silver II oxide specified herein with tNOX offer new and novel therapeutic and diagnostic opportunities including but not restricted to coupling with one or more commercially available silver enhancement protocols for cancer detection as well as detection of an age-related ECTO-NOX form, designated ar-NOX.

摘要翻译： 银（II）氧化物优先与tNOX反应癌细胞表面的癌特异性ECTO-NOX蛋白。 tNOX的癌症特异性与本文所述的银II氧化物与tNOX的相互作用的组合提供了新的和新颖的治疗和诊断机会，包括但不限于与一种或多种市售的用于癌症检测的银增强方案的偶联以及检测 年龄相关的ECTO-NOX形式，指定为ar-NOX。

公开(公告)号：US5420524A

公开(公告)日：1995-05-30

申请号：US157242

申请日：1993-11-26

申请人： Stephen Webster

发明人： Stephen Webster

IPC分类号： H01L27/06 ,  H01L21/8222 ,  H03F1/08 ,  H03F3/45 ,  H03K19/0175 ,  H03K19/086 ,  H03K19/003

CPC分类号： H03F3/4556 ,  H03F1/083 ,  H03F3/45098 ,  H03F2203/45416 ,  H03F2203/45458 ,  H03F2203/45702

摘要： An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor. The third and fourth capacitor structures are located at a second spaced relationship from the substrate. The third capacitor is connected to the first capacitor and the connection forms a first node. The fourth capacitor is connected to the second capacitor and the connection forms a second node. The differential gain stage also includes first and second buffers. The first buffer has an input connected to the non-inverting input of the gain stage and an output connected to the first node. The second buffer has an input connected to the inverting input of the gain stage and an output connected to the second node.

摘要翻译： 用于双极单片集成电路的改进的差分增益级。 集成电路由半导体衬底形成，差分增益级包括第一和第二双极晶体管。 第一晶体管的基极和第二晶体管的基极分别形成用于增益级的差分输入，包括非反相和反相输入。 晶体管的集电极形成差分输出。 差分增益级包括电容器级，包括：峰值电容器，以及第一，第二，第三和第四电容器结构。 峰值电容器耦合在第一和第二晶体管的发射极之间。 第一和第二电容器结构位于与衬底之间的第一间隔关系处，并且第一电容器耦合到第一晶体管的发射极，而第二电容耦合到第二晶体管的发射极。 第三和第四电容器结构位于与衬底之间的第二间隔关系。 第三电容器连接到第一电容器，并且连接形成第一节点。 第四电容器连接到第二电容器，并且连接形成第二节点。 差分增益级还包括第一和第二缓冲器。 第一缓冲器具有连接到增益级的同相输入的输入端和连接到第一节点的输出。 第二缓冲器具有连接到增益级的反相输入的输入端和连接到第二节点的输出。

公开(公告)号：US20080099639A1

公开(公告)日：2008-05-01

申请号：US11978504

申请日：2007-10-29

申请人： Stephen Webster

发明人： Stephen Webster

IPC分类号： A47B91/00

CPC分类号： A47B91/06 ,  A47B2091/063 ,  A47C7/002

摘要： A hook and loop detachable and re-attachable pad apparatus that is applied to furniture to protect flooring surfaces and make sliding furniture easier, has a hook material on a plate that attaches to the furniture to which a separate loop pad, made of loop material, attaches. The loop pad is detachable and re-attachable and may have loop material on both sides. Alternatively, a loop plate applied with loop material may attach to the furniture and have a separate, hook and loop combination pad that attaches to it. The combination pad has one side that is hook material and one side that is loop material so that additional hook and loop combination pads may be stacked on top of the prior pad to provide a thicker cushion to account for pad compression due to heavier pieces of furniture or to slightly raise pieces of furniture to better suit a user.

摘要翻译： 适用于家具以保护地板表面并使滑动家具更容易的钩和环可拆卸和可重新附接的垫装置在板上具有连接到家具的钩材料，由环材料制成的单独的环垫， 附上 环垫可拆卸并可重新连接，并且可以在两侧具有环形材料。 或者，施加有环材料的环板可以附接到家具并且具有附接到其的单独的钩环组合垫。 组合垫具有一侧是钩材料，一侧是环形材料，使得附加的钩和环组合垫可以堆叠在现有垫的顶部上，以提供较厚的垫，以解释由于较重的家具造成的垫压缩 或稍微升高家具件以更好地适应用户。

公开(公告)号：US20060016603A1

公开(公告)日：2006-01-26

申请号：US10504882

申请日：2003-02-14

申请人： Stephen Webster ,  Paul McClure

发明人： Stephen Webster ,  Paul McClure

IPC分类号： E21B29/00

CPC分类号： E21B29/06 ,  E21B7/067

摘要： Apparatus and methods for drilling out from a casing string in a borehole. A reaming assembly is introduced into the borehole and fixed at a predetermined location. A drillable collar is interposed between the reaming assembly and a casing. A drilling assembly introduced into the casing and is then positioned so as to drill through the drillable collar at a predetermined angle into a formation surrounding the borehole.

摘要翻译： 用于从钻孔中的套管柱钻出的装置和方法。 将扩孔组件引入钻孔中并固定在预定位置。 可钻的套环插入在铰孔组件和套管之间。 将钻进组件引入到壳体中，然后定位成以预定角度穿过可钻取的套环进入围绕钻孔的地层中。

公开(公告)号：US5426389A

公开(公告)日：1995-06-20

申请号：US6397

申请日：1993-01-21

申请人： Stephen Webster

发明人： Stephen Webster

IPC分类号： H03K5/007 ,  H04B3/14 ,  H04L25/03 ,  H04L25/06 ,  H03K5/01

CPC分类号： H04L25/061 ,  H03K5/007

摘要： A device for restoring DC and non-zero average components of a serially transmitted binary signal which has been AC coupled. The device comprises an input port for the binary signal, a clamping circuit, a feedback network, a summing node, and an output port. The input port includes a capacitor for coupling the binary signal to the summing node and the clamping circuit. The feedback network includes an input and an output which are also connected to the summing node. The clamping circuit clamps the positive and negative peaks of the AC coupled binary signal which exceed a predetermined range. The feedback network latches the AC coupled binary signal and produces a current signal. For a binary signal which is within the predetermined range, the clamping circuit exhibits a very high input impedance, thereby causing the current signal to charge the coupling capacitor and produce a voltage which is added to the AC coupled binary signal at the summing node. The output port includes a comparator which converts the restored AC coupled binary signal to digital logic levels. In another embodiment, the clamping circuit includes a current sensor for producing an amplitude signal which is indicative of the amplitude of the AC coupled binary signal. The amplitude signal is fed to an automatic gain controller which produces a gain control voltage for controlling the operation of a high frequency equalizer.

摘要翻译： 一种用于恢复已经被AC耦合的串行传输的二进制信号的DC和非零平均分量的装置。 该装置包括用于二进制信号的输入端口，钳位电路，反馈网络，求和节点和输出端口。 输入端口包括用于将二进制信号耦合到求和节点和钳位电路的电容器。 反馈网络包括也连接到求和节点的输入和输出。 钳位电路钳位超过预定范围的AC耦合二进制信号的正峰值和负峰值。 反馈网络锁存交流耦合二进制信号并产生电流信号。 对于处于预定范围内的二进制信号，钳位电路表现出非常高的输入阻抗，从而使电流信号对耦合电容器充电，并产生一个电压，该电压加到求和节点处的交流耦合二进制信号。 输出端口包括将恢复的AC耦合二进制信号转换为数字逻辑电平的比较器。 在另一个实施例中，钳位电路包括用于产生指示AC耦合二进制信号的幅度的振幅信号的电流传感器。 幅度信号被馈送到自动增益控制器，该自动增益控制器产生用于控制高频均衡器的操作的增益控制电压。