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8 条记录 (耗时 0.028 秒)

    Battery system
    1.
    发明授权
    Battery system 失效
    电池系统

    公开(公告)号：US08021773B1

    公开(公告)日：2011-09-20

    申请号：US12052362

    申请日：2008-03-20

    申请人： Steve D. Simon ,  Victor A. Lifton ,  Nathalie Pereira ,  Glenn G. Amatucci

    发明人： Steve D. Simon ,  Victor A. Lifton ,  Nathalie Pereira ,  Glenn G. Amatucci

    IPC分类号： H01M10/50 ,  H01M2/00 ,  H01M10/48 ,  H01M6/42

    CPC分类号： H01M10/4207 ,  H01M10/486 ,  H01M16/00

    摘要： A battery system for efficiently operating a battery under various circumstances, such as relating to extreme temperature ranges and varying load (i.e. current) ranges. The battery system generally includes at least one first cell having a first chemistry, at least one second cell having a second chemistry and a controller in communication with the first cell and the second cell. The controller is adapted to employ a chemical reaction of the first chemistry in the first cell or the second chemistry in the second cell. The first chemistry is different than the second chemistry, wherein the first chemistry and the second chemistry may be adapted to provide current over varying temperature ranges or to provide current for varying current loads.

    摘要翻译： 一种用于在各种情况下有效地操作电池的电池系统，例如与极端温度范围和变化负载（即电流）相关的范围。 电池系统通常包括具有第一化学物质的至少一个第一电池，具有第二化学物质的至少一个第二电池和与第一电池和第二电池连通的控制器。 控制器适于采用第一电池中的第一化学物质或第二电池中的第二化学物质的化学反应。 第一化学不同于第二化学，其中第一化学和第二化学可以适于提供电流超过变化的温度范围或为改变电流负载提供电流。

    Digital phase-locked loop for clock recovery
    8.
    发明授权
    Digital phase-locked loop for clock recovery 失效
    用于时钟恢复的数字锁相环

    公开(公告)号：US5937021A

    公开(公告)日：1999-08-10

    申请号：US848742

    申请日：1997-05-01

    申请人： Nathalie Pereira ,  Bertrand DeBray

    发明人： Nathalie Pereira ,  Bertrand DeBray

    IPC分类号： H03L7/099 ,  H04J3/07 ,  H03D3/24

    CPC分类号： H04J3/073 ,  H03L7/0992

    摘要： The invention relates to a phase-locked loop delivering a recovered clock signal from a reference clock signal F.sub.ref in which some transitions are missing. The loop includes a first divide-by-M frequency divider receiving the clock F.sub.ref and delivering a signal of frequency F.sub.ref /M; a phase comparator providing a phase error signal from the signal of frequency F.sub.ref /M, and the output signal from a second divide-by-M frequency divider; a divide-by-K frequency divider providing a signal of frequency F.sub.k from a local oscillator signal of frequency F.sub.oL receiving the phase error signal as a control signal; an adder-counter of the division ratio p/q receiving the local oscillator signal of frequency F.sub.oL and delivering a signal of frequency F.sub.o equal to F.sub.oL *p/q; a mixer delivering a signal of frequency F.sub.n equal to F.sub.o -F.sub.k on the basis of signal of frequency F.sub.k and the signal of frequency F.sub.o ; and a divide-by-N frequency divider synchronized by F.sub.oL, receiving the signal of frequency F.sub.n, and delivering a recovered clock to the second divide-by-M frequency divider.

    摘要翻译： 本发明涉及一种锁相环路，其从其中缺少一些转换的参考时钟信号Fref传送恢复的时钟信号。 该环路包括接收时钟Fref并传送频率Fref / M的信号的第一分频M分频器; 相位比较器，从频率Fref / M的信号和来自第二除M分频器的输出信号提供相位误差信号; K分频器从接收相位误差信号的频率FoL的本地振荡器信号作为控制信号提供频率Fk的信号; 接收频率FoL的本地振荡器信号的分频比p / q的加法器 - 计数器，并且传送等于FoL * p / q的频率Fo的信号; 根据频率Fk的信号和频率Fo的信号，输出等于Fo-Fk的频率Fn的信号的混合器; 以及由FoL同步的除以N分频器，接收频率Fn的信号，并将恢复的时钟传送到第二分频分频器。