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1.发明申请GENERAL PURPOSE HARDWARE TO REPLACE FAULTY CORE COMPONENTS THAT MAY ALSO PROVIDE ADDITIONAL PROCESSOR FUNCTIONALITY 有权一般用途五金替代可能还会提供附加处理器功能的故障核心组件公开(公告)号：US20110161630A1
公开(公告)日：2011-06-30
申请号：US12647940
申请日：2009-12-28
CPC分类号： G06F9/3885 , G06F9/30196 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F11/2028 , G06F11/2038 , G06F11/2043
摘要： An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to faulty execution units, to the proxy unit. As a result, the proxy unit is able to receive the operations, send them to general purpose hardware for execution, and subsequently write-back the execution results to a register file; it essentially replaces the defective execution unit allowing a processor with defective units to be sold or continue operation.
摘要翻译： 本文描述了用于替换故障核心部件的装置和方法。 提供通用硬件来代替核心管道组件，如执行单元。 在执行单元替换的实施例中，提供代理单元，使得映射逻辑能够将与故障执行单元相对应的指令/操作映射到代理单元。 因此，代理单元能够接收操作，将其发送到通用硬件执行，然后将执行结果写回寄存器文件; 它基本上取代了有缺陷的执行单元，允许出售有缺陷单元的处理器或继续操作。
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2.发明授权General purpose hardware to replace faulty core components that may also provide additional processor functionality 有权通用硬件替代可能还提供额外处理器功能的故障核心组件公开(公告)号：US08914672B2
公开(公告)日：2014-12-16
申请号：US12647940
申请日：2009-12-28
CPC分类号： G06F9/3885 , G06F9/30196 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F11/2028 , G06F11/2038 , G06F11/2043
摘要： An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to faulty execution units, to the proxy unit. As a result, the proxy unit is able to receive the operations, send them to general purpose hardware for execution, and subsequently write-back the execution results to a register file; it essentially replaces the defective execution unit allowing a processor with defective units to be sold or continue operation.
摘要翻译： 本文描述了用于替换故障核心部件的装置和方法。 提供通用硬件来代替核心管道组件，如执行单元。 在执行单元替换的实施例中，提供代理单元，使得映射逻辑能够将与故障执行单元相对应的指令/操作映射到代理单元。 因此，代理单元能够接收操作，将其发送到通用硬件执行，然后将执行结果写回寄存器文件; 它基本上取代了有缺陷的执行单元，允许出售有缺陷单元的处理器或继续操作。
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公开(公告)号：US08171328B2
公开(公告)日：2012-05-01
申请号：US12347961
申请日：2008-12-31
IPC分类号： G06F15/16
CPC分类号： G06F15/16 , G06F11/1407 , G06F11/1641 , G06F11/1658 , G06F11/1683 , G06F11/1691
摘要： Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.
摘要翻译： 公开了使用状态历史同步冗余处理器的发明的实施例。 在一个实施例中，装置包括两个处理器，每个处理器的状态存储器和控制逻辑。 每个处理器都要执行相同的指令。 状态存储器是存储由处理器执行的每个指令的压缩处理器状态信息。 控制逻辑是基于来自状态存储器的条目来同步两个处理器。
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4.发明授权Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system 失效在锁定的双模块冗余系统中减少不可纠正的错误率公开(公告)号：US07747932B2
公开(公告)日：2010-06-29
申请号：US11173835
申请日：2005-06-30
IPC分类号： H03M13/00
CPC分类号： G06F11/165 , G06F11/1641 , G06F11/1658 , G06F11/1683
摘要： Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.
摘要翻译： 公开了用于降低锁定双模块冗余系统中的不可校正错误率的装置和方法的实施例。 在一个实施例中，装置包括两个处理器核，微检查器，全局检验器和故障逻辑。 微检查器是检测来自一个核心中的结构的值是否与另一个核心中的相应结构的值匹配。 全局检查器是检测两个内核之间的锁步失败。 如果存在锁步错误但微检查器检测到不匹配，则故障逻辑是使两个内核重新同步。
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公开(公告)号：US09081688B2
公开(公告)日：2015-07-14
申请号：US12317801
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0817
摘要： In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。 描述和要求保护其他实施例。
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公开(公告)号：US20100169693A1
公开(公告)日：2010-07-01
申请号：US12347961
申请日：2008-12-31
CPC分类号： G06F15/16 , G06F11/1407 , G06F11/1641 , G06F11/1658 , G06F11/1683 , G06F11/1691
摘要： Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.
摘要翻译： 公开了使用状态历史同步冗余处理器的发明的实施例。 在一个实施例中，装置包括两个处理器，每个处理器的状态存储器和控制逻辑。 每个处理器都要执行相同的指令。 状态存储器是存储由处理器执行的每个指令的压缩处理器状态信息。 控制逻辑是基于来自状态存储器的条目来同步两个处理器。
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公开(公告)号：US20100169582A1
公开(公告)日：2010-07-01
申请号：US12317801
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
CPC分类号： G06F12/0842 , G06F12/0817
摘要： In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。 描述和要求保护其他实施例。
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公开(公告)号：US07475321B2
公开(公告)日：2009-01-06
申请号：US11027391
申请日：2004-12-29
CPC分类号： G06F11/0793 , G06F11/0724 , G06F12/0817 , G06F2212/1032 , Y10S707/99933 , Y10S707/99934
摘要： In one embodiment, the present invention includes a system, which may be a multiprocessor system having multiple nodes, each with a processor and a cache. The system may include a directory stored in a memory that includes entries having coherency information. At least one of the nodes may be configured to detect an error in an entry of the directory based on a coherency protocol and a state of a status indicator and presence vector of the entry, and without the storage of error correction or parity information in the entry. In some embodiments, the node may correct the error using state information obtained from other nodes.
摘要翻译： 在一个实施例中，本发明包括一种系统，其可以是具有多个节点的多处理器系统，每个具有处理器和高速缓存。 系统可以包括存储在包括具有一致性信息的条目的存储器中的目录。 节点中的至少一个可以被配置为基于一致性协议和条目的状态指示符和存在向量的状态来检测目录的条目中的错误，并且在不存在错误校正或奇偶校验信息的存储中 条目。 在一些实施例中，节点可以使用从其他节点获得的状态信息来校正错误。
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公开(公告)号：US20110271262A1
公开(公告)日：2011-11-03
申请号：US13135712
申请日：2011-07-13
IPC分类号： G06F9/45
CPC分类号： G06F8/52 , G06F8/53 , G06F11/008
摘要： A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.
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公开(公告)号：US07606980B2
公开(公告)日：2009-10-20
申请号：US11363963
申请日：2006-02-27
IPC分类号： G06F11/08
CPC分类号： G06F12/0804 , G06F11/1064
摘要： A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error correction codes (ECC) while maintaining substantially the same performance of the cache.
摘要翻译： 一种基于需求的纠错技术。 更具体地，本发明的至少一个实施例涉及一种减少包含纠错码（ECC）的高速缓冲存储器的存储开销的技术，同时保持高速缓存的基本相同的性能。
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