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1.再颁专利System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer 有权用于从设备接收用于选择其相关联的时钟信号以控制经由缓冲器传送信息的控制信号的系统公开(公告)号：USRE40317E1
公开(公告)日：2008-05-13
申请号：US09815873
申请日：2001-03-22
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.
摘要翻译： 一种计算机系统，包括响应于第一时钟的定时操作的第一组件，用于存储信息的设备，用于将信息从第一组件传输到利用第一组件的时钟存储信息的设备的设备， 响应于第二时钟的定时，用于利用第二组件的时钟从用于存储信息的设备传送信息的设备在其被同步以供第二组件使用的条件下的设备，由此信息可以被第二时钟的定时利用 第二组件，而不需要由第二组件存储。
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2.发明授权System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer 失效用于从设备接收用于选择其相关联的时钟信号以控制经由缓冲器传送信息的控制信号的系统
公开(公告)号：US5887196A
公开(公告)日：1999-03-23
申请号：US185275
申请日：1994-01-24
CPC分类号： G06F13/4243
摘要： A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.
摘要翻译： 一种计算机系统，包括响应于第一时钟的定时操作的第一组件，用于存储信息的装置，用于将信息从第一组件传送到利用第一组件的时钟存储信息的装置的装置， 响应于第二时钟的定时，用于利用第二组件的时钟从用于存储信息的设备传送信息的设备在其被同步以供第二组件使用的条件下的设备，由此信息可以被第二时钟的定时利用 第二组件，而不需要由第二组件存储。
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3.发明授权Apparatus for providing priority arbitration in a computer system interconnect 失效用于在计算机系统互连中提供优先仲裁的装置
公开(公告)号：US5257385A
公开(公告)日：1993-10-26
申请号：US815825
申请日：1991-12-30
IPC分类号： G06F13/14
CPC分类号： G06F13/14
摘要： A circuit which includes apparatus for determining for at each node of a multi-node interconnect the highest priority data present for transfer to that node, apparatus for storing information indicating the last node from which a transfer of data occurred at each priority level, apparatus for selecting for each priority level of data available at the node the last node from which a transfer of data occurred at each priority level, apparatus for weighting data at each priority level depending on the data last chosen at that level of priority, and means for selecting from all of the data available at each node the data having both the highest priority and having been chosen least recently at that priority levels of data at that node.
摘要翻译： 一种电路，包括用于在多节点互连的每个节点处确定用于传送到该节点的最高优先级数据的装置，用于存储指示在每个优先级级别发生数据传输的最后节点的信息的装置，用于 选择在节点处可用于每个优先级级别的数据传输的最后节点的每个优先级数据的装置，用于根据在该优先级级别最后选择的数据在每个优先级处加权数据的装置，以及用于选择 从每个节点可用的所有数据中，数据具有最高优先级并且最近被选择在该节点处的那个优先级数据。
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4.发明授权System for providing control of data transmission by destination node using stream values transmitted from plural source nodes 失效用于使用从多个源节点发送的流值来提供目的地节点对数据传输的控制的系统
公开(公告)号：US5694545A
公开(公告)日：1997-12-02
申请号：US483831
申请日：1995-06-07
IPC分类号： G06F13/00 , G06F13/18 , H04N7/173 , G06F13/362
CPC分类号： H04N7/17336 , G06F13/18
摘要： Apparatus for allowing a component of a computer system to which data is to be written to control the order of transfer of that data including circuitry for providing a numbered signal signifying that a particular component has a set of data which is to be transferred to the destination component, circuitry associated with the destination component for choosing among all of the numbered signals to select from all sets of data a next set of data in a particular numerical order, and circuitry associated with the destination component for selecting other than the next set of data in the particular numerical order.
摘要翻译： 用于允许要写入数据的计算机系统的组件以控制该数据的传送顺序的装置，包括用于提供编号的信号的电路，该电路指示特定组件具有要传送到目的地的一组数据 与目的地组件相关联的电路，用于在所有编号的信号中选择以从特定数字顺序的下一组数据的所有数据集中选择的电路，以及与用于选择下一组数据的目的地组件相关联的电路 在特定的数字顺序。
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5.发明授权Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed 失效互连系统通过发射总线以源的时钟速度启动数据传输，并以接收机的时钟速度在数据路径上传输数据
公开(公告)号：US5640599A
公开(公告)日：1997-06-17
申请号：US210733
申请日：1994-03-18
CPC分类号： G06F15/17
摘要： A computer interconnect including a plurality of nodes, each node capable of joining to a component of a computer, each node including apparatus for transferring signals between the component and the node, apparatus for storing packets of data, apparatus for signalling each other node that a packet of data exists for transfer to a component associated with that node, apparatus for sensing signals from another node indicating that a packet of data exists for transfer to a component associated with that node, and apparatus for transferring packets of data stored at one node to the apparatus for transferring signals between the component and the node of another node.
摘要翻译： 一种包括多个节点的计算机互连，每个节点能够加入到计算机的组件，每个节点包括用于在组件和节点之间传送信号的装置，用于存储数据分组的装置，用于发信号通知每个其他节点的装置 存在用于传送到与该节点相关联的组件的数据分组的装置，用于感测来自另一个节点的信号的装置，指示存在用于传送到与该节点相关联的组件的数据分组的数据;以及用于将存储在一个节点的数据分组传送到 用于在组件和另一节点的节点之间传送信号的装置。
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6.发明授权Apparatus for translating data formats starting at an arbitrary byte position 失效用于在任意字节位置开始翻译数据格式的装置
公开(公告)号：US5410677A
公开(公告)日：1995-04-25
申请号：US815828
申请日：1991-12-30
CPC分类号： G06F7/762 , G06F13/4018
摘要： A circuit for translating data in one of a plurality of data formats into data in any of the other of the plurality of the data formats including apparatus for storing data from a first number of input bytes of data, apparatus for selecting unused bytes from the first number of data bytes stored by the apparatus for storing data and from a second number of input bytes of data, apparatus for placing the unused bytes selected in numerical byte order, and apparatus for placing the data in the numerical byte order in byte position for transfer to the format of a destination device.
摘要翻译： 一种用于将多种数据格式中的一种数据转换为多种数据格式中的另一种数据格式的数据的电路，包括用于从第一数量的输入字节数据存储数据的装置，用于从第一数据格式中选择未使用字节的装置 用于存储数据的装置和从第二数量的输入字节的数据存储的数据字节的数量，用于放置以数字字节顺序选择的未使用字节的装置，以及用于以数字字节顺序将数据放置在字节位置用于传送的装置 到目标设备的格式。
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7.发明授权Computer system for transferring information streams in a plurality of formats without control information regarding the information streams 失效用于以多种格式传送信息流的计算机系统，而不关于信息流的控制信息
公开(公告)号：US5655091A
公开(公告)日：1997-08-05
申请号：US417400
申请日：1995-04-05
申请人： Dean M. Drako , Steven G. Roskowski
发明人： Dean M. Drako , Steven G. Roskowski
CPC分类号： G09G5/14 , G06F3/1438 , G09G5/363 , G09G5/39
摘要： An arrangement for transmitting information from a first component of a computer system to a second component of the computer system including a source channel associated with the first component of the computer system; a destination channel associated with the second component of the computer system; apparatus for interconnecting the source and the destination channels; the source channel including apparatus for creating a stream of information in a prescribed format, apparatus for designating a destination channel as an address for the stream of information, and apparatus for transferring the stream of information to the apparatus for interconnecting the source and the destination channels; and the destination channel including apparatus for receiving a stream of information in the prescribed format from the apparatus for interconnecting the source and the destination channels, apparatus for receiving control signals apart from the stream of information, and apparatus for controlling the use of the stream of information in response to the control signals.
摘要翻译： 一种用于将信息从计算机系统的第一组件传输到计算机系统的第二组件的装置，包括与计算机系统的第一组件相关联的源通道; 与计算机系统的第二组件相关联的目的地信道; 用于互连源和目的地信道的装置; 源信道包括用于以规定格式创建信息流的装置，用于指定目的信道作为信息流的地址的装置，以及用于将信息流传送到用于互连源和目的信道的装置的装置 ; 并且目的地信道包括用于从用于互连源和目的信道的装置接收规定格式的信息流的装置，用于接收除信息流之外的控制信号的装置，以及用于控制信息流的使用的装置 响应控制信号的信息。
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8.发明授权
公开(公告)号：US5446866A
公开(公告)日：1995-08-29
申请号：US828353
申请日：1992-01-30
申请人： Dean M. Drako , Steven G. Roskowski
发明人： Dean M. Drako , Steven G. Roskowski
CPC分类号： G09G5/14 , G06F3/1438 , G09G5/363 , G09G5/39
摘要： An arrangement for transmitting information from a first component of a computer system to a second component of the computer system including a source channel associated with the first component of the computer system; a destination channel associated with the second component of the computer system; apparatus for interconnecting the source and the destination channels; the source channel including apparatus for creating a stream of information in a prescribed format, apparatus for designating a destination channel as an address for the stream of information, and apparatus for transferring the stream of information to the apparatus for interconnecting the source and the destination channels; and the destination channel including apparatus for receiving a stream of information in the prescribed format from the apparatus for interconnecting the source and the destination channels, apparatus for receiving control signals apart from the stream of information, and apparatus for controlling the use of the stream of information in response to the control signals.
摘要翻译： 一种用于将信息从计算机系统的第一组件传输到计算机系统的第二组件的装置，包括与计算机系统的第一组件相关联的源通道; 与计算机系统的第二组件相关联的目的地信道; 用于互连源和目的地信道的装置; 源信道包括用于以规定格式创建信息流的装置，用于指定目的信道作为信息流的地址的装置，以及用于将信息流传送到用于互连源和目的信道的装置的装置 ; 并且目的地信道包括用于从用于互连源和目的信道的装置接收规定格式的信息流的装置，用于接收除信息流之外的控制信号的装置，以及用于控制信息流的使用的装置 响应控制信号的信息。
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9.发明授权Control apparatus for maintaining order and accomplishing priority promotion in a computer interconnect 失效用于维持计算机互连中的顺序和完成优先级提升的控制装置
公开(公告)号：US5848297A
公开(公告)日：1998-12-08
申请号：US815694
申请日：1991-12-30
IPC分类号： G06F13/362 , H04L29/06 , G06F13/38
CPC分类号： H04L29/06 , G06F13/362
摘要： A circuit for maintaining the order of transmission of information in a computer interconnect including control circuitry for sending a signal from a source of data to a destination for data indicating that data is ready for transfer, the control circuitry comprising a plurality of buffers for storing information relating to the data, the information including information regarding the order in which the information was received by the control circuitry, means for incrementing the information regarding the order in which the information was received by the control circuitry, and apparatus for sending the information relating to the data to the destination for data in the order of receipt by the control circuitry.
摘要翻译： 一种用于维持计算机互连中的信息传输顺序的电路，包括用于从指示数据准备好传送的数据向数据源发送信号的控制电路，所述控制电路包括用于存储信息的多个缓冲器 关于数据的信息，包括关于由控制电路接收信息的顺序的信息的信息，用于递增关于由控制电路接收信息的顺序的信息的装置，以及用于发送与控制电路有关的信息的装置 将数据按照控制电路接收的顺序传送到目的地。
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公开(公告)号：US08509100B2
公开(公告)日：2013-08-13
申请号：US12371204
申请日：2009-02-13
申请人： Steven G. Roskowski
发明人： Steven G. Roskowski
IPC分类号： H04L12/26
CPC分类号： H04L41/0681 , H04L41/5074 , H04W24/08 , H04W24/10
摘要： Systems and methods that automatically collect data associated with system-identified errors as well as data associated with events associated with user-initiated actions. A data collection profile defines data to be collected and a user-initiated trigger. When the user-initiated trigger is sensed, data is collected according to the data collection profile. The collected data can be uploaded immediately, or stored for some period of time before being transmitted to a collection system. A user recognizes an event which may not be recognizable by the system and the user provides an input defined as the user-initiated trigger. Data may be collected for a brief time before, during and a brief time after sensing the user-initiated trigger and may be uploaded to a system. The user may annotate the collected data by explaining the error, after which the explanation is correlated with the collected data.
摘要翻译： 自动收集与系统识别的错误相关联的数据以及与用户启动的操作相关联的事件相关联的数据的系统和方法。 数据收集配置文件定义要收集的数据和用户启动的触发器。 当感测到用户发起的触发时，根据数据收集简档收集数据。 收集的数据可以立即上传，或者存储一段时间后才能发送到收集系统。 用户识别可能不被系统识别的事件，并且用户提供定义为用户发起的触发的输入。 数据可以在感测到用户发起的触发之前，之后和短时间内的短时间内收集，并且可以被上传到系统。 用户可以通过解释错误来注释收集的数据，之后解释与收集的数据相关。
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