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1.发明授权Register files and caches with digital sub-threshold leakage current calibration 有权使用数字子阈值泄漏电流校准来注册文件和缓存公开(公告)号：US06690604B2
公开(公告)日：2004-02-10
申请号：US10024901
申请日：2001-12-18
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： A memory circuit, such as a cache or register file, where the keeper functional units are digitally controlled to compensate for variable sub-threshold leakage current.
摘要翻译： 存储器电路，例如高速缓存或寄存器文件，其中保持器功能单元被数字地控制以补偿可变的亚阈值泄漏电流。
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公开(公告)号：US06441648B1
公开(公告)日：2002-08-27
申请号：US09852442
申请日：2001-05-09
IPC分类号： H03K1901
CPC分类号： H03K19/0963
摘要： A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide the output signals. In another embodiment, two nMOSFET pull-down logic units are employed, each clocked by an nMOSFET in complementary fashion, and a static logic unit provides the output signals.
摘要翻译： 一种双数据速率动态逻辑门，其中对时钟信号的每个相位执行评估阶段。 在一个实施例中，nMOSFET下拉逻辑单元由以互补方式切换的两个nMOSFET计时，并且动态锁存器提供输出信号。 在另一个实施例中，采用两个nMOSFET下拉逻辑单元，每个以互补方式由nMOSFET计时，并且静态逻辑单元提供输出信号。
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3.发明授权Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports 有权在读端口的动态位线中具有降低的亚阈值泄漏电流的存储器公开(公告)号：US06643199B1
公开(公告)日：2003-11-04
申请号：US10162929
申请日：2002-06-04
申请人： Stephen H. Tang , Steven K. Hsu , Vivek K. De , Shih-Lien L. Lu
发明人： Stephen H. Tang , Steven K. Hsu , Vivek K. De , Shih-Lien L. Lu
IPC分类号： G11C700
CPC分类号： G11C11/412
摘要： For a memory cell, where an access transistor couples the memory cell to a local bit line, a pMOSFET essentially eliminates sub-threshold leakage current in the access transistor when the memory cell is not being read, and when the memory cell is being read, an additional pMOSFET essentially eliminates sub-threshold leakage current in the access transistor if the memory cell stores an information bit such that it does not discharge the local bit line. In this way, a half-keeper connected to the local bit line does not need to contend with sub-threshold leakage current.
摘要翻译： 对于存储晶体管，其中存取晶体管将存储单元耦合到局部位线，当存储单元未被读取时，pMOSFET基本上消除了存取晶体管中的次阈值泄漏电流，并且当存储单元被读取时， 如果存储单元存储信息位，使得其不释放局部位线，附加的pMOSFET基本上消除了存取晶体管中的次阈值漏电流。 以这种方式，连接到本地位线的半保持器不需要与亚阈值泄漏电流相抗衡。
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公开(公告)号：US07250783B2
公开(公告)日：2007-07-31
申请号：US11022800
申请日：2004-12-28
IPC分类号： G01R31/02
CPC分类号： G11C29/50 , G01R31/3012 , G11C2029/5004 , G11C2029/5006
摘要： A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.
摘要翻译： 电流镜多通道泄漏监控电路和方法测量管芯泄漏，并产生数字保持器控制位以控制过程补偿动态电路。 泄漏监测器可在芯片上的多个位置进行高分辨率片上泄漏测量，从而节省测试时间，并使裸片和裸片工艺补偿均可实现。
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公开(公告)号：US07016239B2
公开(公告)日：2006-03-21
申请号：US10676985
申请日：2003-09-30
IPC分类号： G11C7/00
摘要： A register file contains a local bit trace and a driving signal trace as well as a plurality of data cells coupled to the local bit trace. A device is coupled to the driving signal trace and the local bit trace to intelligently charge and float the local bit trace. The intelligent charging and floating is facilitated by determination of a selection of one of the data cells.
摘要翻译： 寄存器文件包含本地位跟踪和驱动信号跟踪以及耦合到本地位跟踪的多个数据单元。 一个器件耦合到驱动信号跟踪和本地位跟踪，以智能地对本地位跟踪进行充电和浮动。 通过确定数据单元之一的选择来促进智能充电和浮动。
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6.发明授权Robust variable keeper strength process-compensated dynamic circuit and method 有权鲁棒可变门限强度过程补偿动态电路及方法公开(公告)号：US07002375B2
公开(公告)日：2006-02-21
申请号：US10401774
申请日：2003-03-31
IPC分类号： H03K19/096 , H03K17/16 , H03K19/003
CPC分类号： H03K19/0963
摘要： A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.
摘要翻译： 基于可变门限强度的过程补偿动态电路和方法提供了一种鲁棒的数字方式来克服制造的模具中存在的固有参数变化。 使用过程补偿动态电路，广泛的鲁棒性和延迟分布变窄，从而提高性能，而不会牺牲最坏情况的鲁棒性。 保持器的强度根据模具泄漏量进行编程。 守门员将具有最佳和最差情况泄漏的最佳强度，从而改善最坏情况下的鲁棒性。
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公开(公告)号：US06628557B2
公开(公告)日：2003-09-30
申请号：US09966193
申请日：2001-09-28
申请人： Steven K. Hsu , Ram Krishnamurthy
发明人： Steven K. Hsu , Ram Krishnamurthy
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/419
摘要： The present invention is in the area of memory architecture. More particularly, the present invention provides a method, apparatus, machine-readable medium, and system reduce leakage current in memory. Embodiments may take advantage of the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, within the memory to limit leakage and provide for a leakage tolerant data storage technique. Embodiments may also enable the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, to be taken advantage of by sourcing charge from data storage elements.
摘要翻译： 本发明在存储器架构的领域。 更具体地说，本发明提供一种方法，装置，机器可读介质和系统减少存储器中的泄漏电流。 实施例可以利用电路元件的反向偏置特性，例如存储器内的晶体管的反向栅极到源极偏置特性，以限制泄漏并提供泄漏容限数据存储技术。 实施例还可以使电路元件的反向偏置特性（例如晶体管的反向栅极 - 源极偏置特性）被利用来从数据存储元件中提取电荷。
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公开(公告)号：US07362621B2
公开(公告)日：2008-04-22
申请号：US10676276
申请日：2003-09-30
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C7/12 , G11C2207/104
摘要： A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selectively decouple the driving signal trace from said global bit trace.
摘要翻译： 寄存器文件包括多电平多路复用器输出电路，其耦合到耦合到所述全局位线跟踪和驱动信号迹线的全局位跟踪和保持器电路。 寄存器文件还具有耦合到所述保持器电路的解码器电路，以选择性地将驱动信号迹线与所述全局位线分离。
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9.发明授权Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation 失效多电源电压拉链CMOS逻辑系列具有低有源漏电功耗公开(公告)号：US06693461B2
公开(公告)日：2004-02-17
申请号：US10027292
申请日：2001-12-20
申请人： Steven K. Hsu , Ram Krishnamurthy
发明人： Steven K. Hsu , Ram Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment zipper circuit achieves reduced leakage current by utilizing four voltages so that FETs in the p-logic blocks and n-logic blocks are reversed biased during a pre-charge phase. The FETs in a logic block are also reversed biased during an evaluation phase if the input voltages to the logic block are such that the logic block is not driven ON during the evaluation phase.
摘要翻译： 实施例拉链电路通过利用四个电压来实现减小的漏电流，使得在预充电阶段期间p逻辑块和n逻辑块中的FET被反向偏置。 如果逻辑块的输入电压使得在评估阶段期间逻辑块不被驱动为ON，则逻辑块中的FET在评估阶段也被反向偏置。
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10.发明申请Multiplier product generation based on encoded data from addressable location 有权基于可寻址位置的编码数据的乘数乘积生成公开(公告)号：US20080098278A1
公开(公告)日：2008-04-24
申请号：US11540346
申请日：2006-09-29
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F7/533 , G06F7/5332 , G06F7/5334 , G06F7/74
摘要： For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，装置包括至少部分地基于对应于第一号码的地址从可寻址位置输出编码数据的第一电路，其中编码数据至少部分地基于对应于第一号码的数据 并且其被编码用于部分产品减少，以及第二电路，用于至少部分地基于编码数据和对应于第二数量的数据来生成产品。 还公开了其他实施例。
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