公开(公告)号：US07382157B1

公开(公告)日：2008-06-03

申请号：US11541986

申请日：2006-10-02

申请人： Steven P. Young ,  Ramakrishna K. Tanikella ,  Manoj Chirania ,  Venu M. Kondapalli

发明人： Steven P. Young ,  Ramakrishna K. Tanikella ,  Manoj Chirania ,  Venu M. Kondapalli

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K17/693 ,  H03K19/17728

摘要： Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driver circuits coupled between the logic circuits. Each self-resetting interconnect driver circuit includes a multiplexer circuit driving a buffer circuit. In a first state, the buffer circuit drives a first value onto the output terminal of the buffer circuit. In a second state, the buffer circuit first drives a second value onto the output terminal of the buffer circuit and then returns to the first state. Several different circuits are described in detail.

摘要翻译： 互连驱动电路，可用于动态集成电路（IC）的互连结构，如动态可编程逻辑器件（PLD）。 示例性IC包括两个或多个逻辑电路和耦合在逻辑电路之间的两个或多个自复位互连驱动器电路。 每个自复位互连驱动器电路包括驱动缓冲电路的多路复用器电路。 在第一状态下，缓冲电路将第一值驱动到缓冲电路的输出端上。 在第二状态下，缓冲电路首先将第二值驱动到缓冲电路的输出端，然后返回到第一状态。 详细描述了几个不同的电路。

公开(公告)号：US07215138B1

公开(公告)日：2007-05-08

申请号：US11152590

申请日：2005-06-14

申请人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

发明人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/1736 ,  H03K19/17728 ,  H03K19/1776

摘要： A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N−1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N−2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.

摘要翻译： 用于集成电路（IC）的可编程查找表可选地在编程为用作移位寄存器逻辑时提供两个输入信号和两个输出信号到可编程IC的互连结构。 根据一个实施例，集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT），其中N是整数。 LUT可以被配置为用作具有输入信号移位和耦合到互连结构的一个输出信号的（2 **（N-1））位移位寄存器，或者作为二（2 **（N- 2）） - 具有耦合到互连结构的输入信号中的两个移位和两个输出信号的位移位寄存器。 在一些实施例中，移位寄存器的每个位包括LUT的两个存储单元，用作主锁存器的第一存储器单元和用作从锁存器的第二存储器单元。

公开(公告)号：US07375552B1

公开(公告)日：2008-05-20

申请号：US11151892

申请日：2005-06-14

申请人： Steven P. Young ,  Trevor J. Bauer ,  Manoj Chirania ,  Venu M. Kondapalli

发明人： Steven P. Young ,  Trevor J. Bauer ,  Manoj Chirania ,  Venu M. Kondapalli

IPC分类号： H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17736 ,  G06F7/5324 ,  G06F7/5443 ,  H03K19/17728

摘要： A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.

摘要翻译： 可编程逻辑块向集成电路（IC）中的通用互连结构提供两个查找表（LUT）输出信号，逻辑块的一个输出端专用于第一LUT输出信号，另一个输出端具有可选择的 可以将两个LUT输出信号中的任一个提供给通用互连结构的输入。 IC包括互连结构（例如，可编程互连结构）和耦合到互连结构的可编程逻辑块。 可编程逻辑块包括具有两个输出端的LUT。 第一LUT输出端子经由逻辑块的第一输出端子不可编程地耦合到互连结构。 第一和第二LUT输出端子都可以通过逻辑块的第二输出端子可编程地耦合到互连结构，例如经由可编程多路复用器在两个LUT输出端子之间进行选择。

公开(公告)号：US07265576B1

公开(公告)日：2007-09-04

申请号：US11152736

申请日：2005-06-14

申请人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

发明人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)×1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N−1))×2 RAM) having fewer than N (e.g., N−1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N−1)-bit shift register or two 2**(N−2)-bit shift registers.

摘要翻译： 当编程为用作随机存取存储器（RAM）时，可编程查找表可选地向可编程集成电路的互连结构提供两个输入信号和两个输出信号。 集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT）。 LUT可以被配置为用作具有耦合到互连结构的N个输入地址信号和耦合到互连结构的一个输出信号的单位宽RAM（例如，（2 ** N）x1 RAM），或者作为 具有小于N（例如，N-1）个输入地址信号的耦合到互连结构的多位宽RAM（例如，（2 **（N-1））×2 RAM）以及耦合到互连结构的至少两个输出信号 互连结构。 可选地，LUT也可以被配置为移位寄存器逻辑，例如2 **（N-1）位移位寄存器或两个2 **（N-2）位移位寄存器。

公开(公告)号：US07268587B1

公开(公告)日：2007-09-11

申请号：US11152012

申请日：2005-06-14

申请人： Tien Pham ,  Manoj Chirania ,  Venu M. Kondapalli ,  Steven P. Young

发明人： Tien Pham ,  Manoj Chirania ,  Venu M. Kondapalli ,  Steven P. Young

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17728

摘要： A programmable logic block provides N-bit and M-bit (e.g., (N/2)-bit) lookahead functionality for carry chains traversing the logic block, N and M being integers greater than one. An exemplary programmable logic block includes four carry multiplexers that together form a 4-bit lookahead carry chain. The 4-bit lookahead carry chain also provides a 2-bit lookahead output after the second carry multiplexer. Alternatively, the last two bits of the 4-bit lookahead carry chain can be used as a 2-bit lookahead carry chain. In one embodiment, the programmable logic block also includes four function generators associated with the four carry multiplexers. Each function generator drives a select terminal of the associated carry multiplexer. The 4-bit and 2-bit carry chains can be programmably coupled to an interconnect structure of the PLD at the carry out output terminals. In some embodiments, an initialization value can also be provided to the 4-bit and 2-bit carry chains.

摘要翻译： 可编程逻辑块为穿越逻辑块的进位链提供N位和M位（例如，（N / 2）位）前瞻功能，N和M是大于1的整数。 示例性可编程逻辑块包括四个进位多路复用器，它们一起形成4位前置进位链。 4位前置进位链还提供了第二个进位多路复用器后的2位前置输出。 或者，4位前瞻进位链的最后两位可以用作2位前瞻进位链。 在一个实施例中，可编程逻辑块还包括与四个进位多路复用器相关联的四个功能发生器。 每个功能发生器驱动相关进位多路复用器的选择端。 4位和2位进位链可以可编程地耦合到进位输出端的PLD的互连结构。 在一些实施例中，还可以向4位和2位进位链提供初始化值。

公开(公告)号：US07202697B1

公开(公告)日：2007-04-10

申请号：US11152737

申请日：2005-06-14

申请人： Venu M. Kondapalli ,  Manoj Chirania

发明人： Venu M. Kondapalli ,  Manoj Chirania

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/17728

摘要： A programmable logic block reduces output delay by bypassing a final slave latch when programmed to function as a shift register. The logic block includes memory cells, a multiplexer structure, and a bypass select multiplexer (BSM). The memory cells are coupled in series to form a shift register controlled by a shift clock, each bit including two paired memory cells implementing master and slave latches. Each memory cell drives an input terminal of the multiplexer structure. The BSM drives a select terminal of the multiplexer structure and selects one signal from each pair of the memory cells. The shift clock drives one data input terminal of the BSM. When in shift register mode, the shift clock simultaneously shifts a value in each master latch to the corresponding slave latch and selects a value from one of the master latches. The output path bypasses the slave latch of the selected bit.

摘要翻译： 当编程为用作移位寄存器时，可编程逻辑块通过绕过最终从锁存器来减少输出延迟。 逻辑块包括存储器单元，多路复用器结构和旁路选择多路复用器（BSM）。 存储器单元串联耦合以形成由移位时钟控制的移位寄存器，每个位包括实现主锁存器和从锁存器的两个配对存储器单元。 每个存储单元驱动多路复用器结构的输入端。 BSM驱动多路复用器结构的选择端，并从每对存储单元中选择一个信号。 移位时钟驱动BSM的一个数据输入端。 在移位寄存器模式下，移位时钟同时将每个主锁存器中的值移位到相应的从锁存器，并从其中一个主锁存器中选择一个值。 输出路径旁路所选位的从锁存器。

公开(公告)号：US07804719B1

公开(公告)日：2010-09-28

申请号：US11151939

申请日：2005-06-14

申请人： Manoj Chirania ,  Venu M. Kondapalli

发明人： Manoj Chirania ,  Venu M. Kondapalli

IPC分类号： G11C7/00

CPC分类号： H03K19/1776 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable logic block provides an improved output delay by bypassing the memory array and multiplexer structure when programmed to function as a random access memory (RAM) and a new value is written to the RAM. A programmable logic block includes memory cells, a multiplexer structure, a memory element, a bypass select multiplexer, and a control circuit. The memory cells implement a RAM driven by a write data input signal and a write enable signal. Each memory cell drives an input terminal of the multiplexer structure. Under the control of the write enable signal, a bypass select multiplexer selects either the write data input signal (in RAM mode) or the output terminal of the multiplexer structure (in another mode), and passes the selected signal to a memory element. Thus, when in RAM mode, write data is simultaneously written to a specified location in the RAM and to the memory element.

摘要翻译： 当编程为用作随机存取存储器（RAM）并且将新值写入RAM时，可编程逻辑块通过绕过存储器阵列和多路复用器结构来提供改进的输出延迟。 可编程逻辑块包括存储器单元，多路复用器结构，存储元件，旁路选择多路复用器和控制电路。 存储单元实现由写数据输入信号和写使能信号驱动的RAM。 每个存储单元驱动多路复用器结构的输入端。 在写使能信号的控制下，旁路选择多路复用器选择写入数据输入信号（以RAM模式）或多路复用器结构的输出端（在另一模式中），并将选择的信号传递到存储元件。 因此，当在RAM模式中，写入数据被同时写入RAM中的指定位置和存储元件。

公开(公告)号：US07116131B1

公开(公告)日：2006-10-03

申请号：US10941607

申请日：2004-09-15

申请人： Manoj Chirania ,  Venu M. Kondapalli

发明人： Manoj Chirania ,  Venu M. Kondapalli

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K17/693 ,  H03K19/17728

摘要： A programmable logic device (PLD) includes dynamic lookup table (LUT) circuits, an interconnect structure implemented in either dynamic or static logic, and optional static logic circuits. Each dynamic LUT circuit has paired true and complement input terminals and provides to the interconnect structure both true and complement output signals pre-charged to a first known value. In some embodiments, the LUT circuits are self-resetting circuits that detect when the paired input signals are valid and evaluate the LUT output values at that time. Once a valid LUT output value has been produced, the LUT resets itself in anticipation of the next valid input condition. In some embodiments, the LUT circuits are implemented using clocked dynamic logic. Routing multiplexers in the interconnect structure can be static or dynamic logic, optionally skewed. Clocked LUTs and routing multiplexers use either of two clock phases under the control of configuration memory cells of the PLD.

摘要翻译： 可编程逻辑器件（PLD）包括动态查找表（LUT）电路，以动态或静态逻辑实现的互连结构以及可选的静态逻辑电路。 每个动态LUT电路具有成对的真实和补码输入端子，并且向互连结构提供预充电到第一已知值的真实和补码输出信号。 在一些实施例中，LUT电路是检测成对输入信号何时有效并且评估那时的LUT输出值的自复位电路。 一旦产生了有效的LUT输出值，则LUT将预期下一个有效输入条件自身重置。 在一些实施例中，使用时钟动态逻辑来实现LUT电路。 互连结构中的路由多路复用器可以是静态或动态逻辑，可选地偏斜。 时钟LUT和路由多路复用器在PLD的配置存储单元的控制下使用两个时钟相位中的任一个。

公开(公告)号：US06998872B1

公开(公告)日：2006-02-14

申请号：US10859836

申请日：2004-06-02

申请人： Manoj Chirania ,  Venu M. Kondapalli

发明人： Manoj Chirania ,  Venu M. Kondapalli

IPC分类号： H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/1736 ,  H03K19/1737

摘要： Lookup table (LUT) circuits can optionally be configured as two or more smaller LUTs having independent input signals. A LUT circuit includes a tristate buffer circuit coupled between first and second multiplexer stages. The data input of the tristate buffer circuit is provided as a first output signal from the LUT circuit. The output of the second multiplexer stage provides the second LUT output signal. The tristate buffer circuit can include a tristate buffer with a pullup and a pulldown on the output terminal. To configure the circuit as a single LUT, the buffer is enabled (tristate disabled), and both the pullup and pulldown are turned off. To configure the circuit as two separate LUTs, the buffer is tristated and either the pullup or the pulldown is enabled. Additional multiplexer stages and tristate buffer circuits can be included to enable the division of the circuit into larger numbers of LUTs.

摘要翻译： 查找表（LUT）电路可以可选地被配置为具有独立输入信号的两个或更多个较小的LUT。 LUT电路包括耦合在第一和第二多路复用器级之间的三态缓冲器电路。 三态缓冲电路的数据输入被提供为来自LUT电路的第一输出信号。 第二多路复用器级的输出提供第二LUT输出信号。 三态缓冲电路可以包括在输出端上具有上拉和下拉的三态缓冲器。 要将电路配置为单个LUT，缓冲区将被使能（三态禁用），上拉和下拉都关闭。 要将电路配置为两个独立的LUT，缓冲区被三态化，并且上拉或下拉都被使能。 可以包括附加的多路复用器级和三态缓冲器电路，以使得能够将电路划分成更大数量的LUT。

公开(公告)号：US07119570B1

公开(公告)日：2006-10-10

申请号：US10836850

申请日：2004-04-30

申请人： Manoj Chirania ,  Venu M. Kondapalli ,  Martin L. Voogel ,  Philip Costello

发明人： Manoj Chirania ,  Venu M. Kondapalli ,  Martin L. Voogel ,  Philip Costello

IPC分类号： G01R31/26

CPC分类号： G01R31/31708 ,  G01R31/31725

摘要： A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.

摘要翻译： 用于测试半导体器件上升延迟/下降延迟性能的测试电路可以包括锁存器，用于响应于时钟信号在其输入端锁存数据。 锁存器可以输出与被锁存的数据相关的输出信号。 作为时钟信号，缓冲链可以被配置为将由锁存器产生的信号从锁存器输出串行传播回到时钟输入。 锁存器的复位/置位输入可被配置为从缓冲器链的中间节点接收复位/置位信号。