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1.发明授权Integrated circuits including a charge pump circuit and operating methods thereof 有权包括电荷泵电路的集成电路及其操作方法公开(公告)号：US08183913B2
公开(公告)日：2012-05-22
申请号：US12706886
申请日：2010-02-17
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译： 集成电路包括第一电流源。 第二电流源经由导线与第一电流源电耦合。 开关电路耦合在第一电流源和第二电流源之间。 第一电路耦合在第一节点和第二节点之间。 第一节点设置在第一电流源和开关电路之间。 第二节点与第一电流源耦合。 第一电路被配置为基本上均衡第一节点和第二节点上的电压。 第二电路耦合在第三节点和第四节点之间。 第三节点设置在第二电流源和开关电路之间。 第四节点被布置成与第二电流源耦合。 第二电路被配置为基本上均衡第三节点和第四节点上的电压。
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公开(公告)号：US08575966B2
公开(公告)日：2013-11-05
申请号：US13718235
申请日：2012-12-18
摘要： A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.
摘要翻译： 操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。 确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。 响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。 电荷泵电路根据上升信号和下降信号进行驱动。
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公开(公告)号：US08354862B2
公开(公告)日：2013-01-15
申请号：US13448878
申请日：2012-04-17
IPC分类号： H03D13/00
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译： 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。
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公开(公告)号：US08179162B2
公开(公告)日：2012-05-15
申请号：US12835130
申请日：2010-07-13
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译： 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。
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公开(公告)号：US08575998B2
公开(公告)日：2013-11-05
申请号：US12825652
申请日：2010-06-29
申请人： Ming-Chieh Huang , Tien-Chun Yang , Steven Swei
发明人： Ming-Chieh Huang , Tien-Chun Yang , Steven Swei
摘要： A voltage reference circuit with temperature compensation includes a power supply, a reference voltage supply, a first PMOS transistor with its source connected to the power supply voltage, a second PMOS transistor with its source connected to the power supply and its gate and drain connected to the first PMOS gate, a first NMOS transistor with its gate and drain connected the first PMOS drain, a second NMOS transistor with its drain connected to the second PMOS drain and its gate connected with the first NMOS gate to the reference voltage supply, a resistor connected to the second NMOS source and ground, and an op-amp with its inverting input and its output connected the first NMOS source and its non-inverting input connected to the ground. In another aspect, a voltage reference circuit output is coupled to an NMOS gate in saturation mode connected to another voltage reference circuit.
摘要翻译： 具有温度补偿的电压参考电路包括电源，参考电压源，其源极连接到电源电压的第一PMOS晶体管，其源极连接到电源的第二PMOS晶体管，其栅极和漏极连接到 第一PMOS栅极，第一NMOS晶体管，其栅极和漏极连接到第一PMOS漏极，第二NMOS晶体管，其漏极连接到第二PMOS漏极，其栅极与第一NMOS栅极连接到参考电压源，电阻器 连接到第二个NMOS源和地，以及一个运算放大器及其反相输入端，其输出端与第一个NMOS源及其非反相输入端连接到地。 在另一方面，电压参考电路输出耦合到连接到另一电压参考电路的饱和模式的NMOS栅极。
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公开(公告)号：US20100215139A1
公开(公告)日：2010-08-26
申请号：US12699458
申请日：2010-02-03
申请人： Chih-Chang LIN , Tien-Chun Yang , Steven Swei
发明人： Chih-Chang LIN , Tien-Chun Yang , Steven Swei
IPC分类号： H03K23/00
CPC分类号： H03K21/38
摘要： Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.
摘要翻译： 本文描述的实施例涉及计数器。 在一些实施例中，计数器可以用作分频器，例如在分数PLL中。 在一些实施例中，计数器（例如，主计数器或计数器C）包括第一计数器（例如，计数器C1）和第二计数器（例如，计数器C2），其与第一计数器C1一起执行计数功能 对于计数器C.例如，如果计数器C计数到值N，则计数器C1计数，例如，到N1，并且计数器C2计数到N2，其中N = N1 + N2。 对于计数器C1计数到N1，N1被加载到计数器C1。 类似地，对于计数器C2计数到N2，N2被加载到计数器C2。 当计数器C1计数（例如，到N1）时，可以将N2加载到计数器C2。 在计数器C1结束计数到N1之后，N2（如果加载）可用于计数器C2开始计数到这个N2。 计数器C1和C2可以交替地计数并因此为计数器C提供连续计数。还公开了其他实施例和示例性应用。
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公开(公告)号：US08068576B2
公开(公告)日：2011-11-29
申请号：US12699458
申请日：2010-02-03
申请人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
发明人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
IPC分类号： H03K21/00
CPC分类号： H03K21/38
摘要： Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.
摘要翻译： 本文描述的实施例涉及计数器。 在一些实施例中，计数器可以用作分频器，例如在分数PLL中。 在一些实施例中，计数器（例如，主计数器或计数器C）包括第一计数器（例如，计数器C1）和第二计数器（例如，计数器C2），其与第一计数器C1一起执行计数功能 对于计数器C.例如，如果计数器C计数到值N，则计数器C1计数，例如，到N1，并且计数器C2计数到N2，其中N = N1 + N2。 对于计数器C1计数到N1，N1被加载到计数器C1。 类似地，对于计数器C2计数到N2，N2被加载到计数器C2。 当计数器C1计数（例如，到N1）时，可以将N2加载到计数器C2。 在计数器C1结束计数到N1之后，N2（如果加载）可用于计数器C2开始计数到这个N2。 计数器C1和C2可以交替地计数并因此为计数器C提供连续计数。还公开了其他实施例和示例性应用。
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公开(公告)号：US08475039B2
公开(公告)日：2013-07-02
申请号：US12764532
申请日：2010-04-21
申请人： Chan-Hong Chern , Steven Swei
发明人： Chan-Hong Chern , Steven Swei
CPC分类号： G01K7/14 , G01K7/01 , G01K2219/00
摘要： Mechanisms for providing linear relationship between temperatures and digital codes are disclosed. In one method, at a particular temperature, a circuit in the sensor provides a temperature dependent reference voltage, and a compared voltage, to a comparator. The temperature dependent reference voltage depends on temperature in complement to absolute temperature or alternatively depends on temperature in proportion to absolute temperature. The compared voltage is generated corresponding to digital analog converter (DAC) codes as inputs. Another circuit varies the DAC codes until the temperature dependent reference voltage and the compared voltage are equal so that the dependent reference voltage corresponds to a DAC code. The various temperatures experienced by the temperature sensing circuit and the DAC codes are substantially linearly related.
摘要翻译： 公开了提供温度和数字代码之间的线性关系的机制。 在一种方法中，在特定温度下，传感器中的电路向比较器提供与温度相关的参考电压和比较的电压。 温度依赖参考电压取决于温度与绝对温度的补充，或者取决于与绝对温度成比例的温度。 相应的数字模拟转换器（DAC）代码作为输入产生比较电压。 另一个电路改变DAC代码，直到与温度相关的参考电压和比较的电压相等，从而相关的参考电压对应于DAC代码。 温度感测电路和DAC代码经历的各种温度基本上是线性相关的。
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公开(公告)号：US09004754B2
公开(公告)日：2015-04-14
申请号：US13173112
申请日：2011-06-30
申请人： Steven Swei
发明人： Steven Swei
CPC分类号： G01K7/01 , G01K2219/00
摘要： A thermal sensor includes a comparator having a first and second input nodes. A reference voltage generator is electrically coupled with the first input node. The reference voltage generator is configured to provide a reference voltage that is substantially temperature-independent. A temperature sensing circuit is electrically coupled with the second input node. The temperature sensing circuit is configured to provide a temperature-dependent voltage. The temperature sensing circuit includes a current mirror. A first metal-oxide-semiconductor (MOS) transistor is electrically coupled between the current mirror and ground. A first resistor is electrically coupled with the current mirror. A second MOS transistor is electrically coupled with the first resistor in series. The second MOS transistor and the first resistor are electrically coupled with the first MOS transistor in a parallel fashion.
摘要翻译： 热传感器包括具有第一和第二输入节点的比较器。 参考电压发生器与第一输入节点电耦合。 参考电压发生器被配置为提供基本上与温度无关的参考电压。 温度感测电路与第二输入节点电耦合。 温度感测电路被配置成提供温度依赖电压。 温度检测电路包括电流镜。 第一金属氧化物半导体（MOS）晶体管电耦合在电流镜和地之间。 第一电阻器与电流镜电耦合。 第二MOS晶体管与第一电阻串联电耦合。 第二MOS晶体管和第一电阻器以并行方式与第一MOS晶体管电耦合。
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10.发明授权Memory circuits having a diode-connected transistor with back-biased control 有权存储器电路具有带反向偏置控制的二极管连接晶体管公开(公告)号：US08411525B2
公开(公告)日：2013-04-02
申请号：US12769973
申请日：2010-04-29
申请人： Steven Swei , David B. Scott
发明人： Steven Swei , David B. Scott
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/148 , G11C11/413
摘要： A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor.
摘要翻译： 存储电路包括至少一个存储器阵列。 至少一个睡眠晶体管电耦合在所述至少一个存储器阵列和用于提供第一电源电压的第一电源线之间。 至少一个二极管连接的晶体管电耦合在至少一个存储器阵列和第一电力线之间。 背偏置电路与至少一个二极管连接的晶体管的大部分电耦合。
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