METHODS FOR FORMING A GERMANIUM ISLAND USING SELECTIVE EPITAXIAL GROWTH AND A SACRIFICIAL FILLING LAYER

    公开(公告)号:US20210343528A1

    公开(公告)日:2021-11-04

    申请号:US17289205

    申请日:2018-11-09

    Applicant: STRATIO

    Abstract: A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed.

    Gate-controlled Charge Modulated Device for CMOS Image Sensors

    公开(公告)号:US20190221595A1

    公开(公告)日:2019-07-18

    申请号:US16167241

    申请日:2018-10-22

    Applicant: Stratio Inc.

    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

    SPECTROMETERS WITH SELF-COMPENSATION OF MISALIGNMENT

    公开(公告)号:US20200256731A1

    公开(公告)日:2020-08-13

    申请号:US16859941

    申请日:2020-04-27

    Applicant: Stratio

    Abstract: An apparatus for analyzing light includes an input aperture for receiving light; a first set of one or more lenses configured to relay light from the input aperture; and a prism assembly configured to disperse light from the first set of one or more lenses. The prism assembly includes a plurality of prisms that includes a first prism, a second prism that is distinct from the first prism, and a third prism that is distinct from the first prism and the second prism. The first prism is mechanically coupled with the second prism and the second prism is mechanically coupled with the third prism. The apparatus also includes a second set of one or more lenses configured to focus the dispersed light from the prism assembly; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals.

    Gate-Controlled Charge Modulated Device for CMOS Image Sensors

    公开(公告)号:US20230019977A1

    公开(公告)日:2023-01-19

    申请号:US17684124

    申请日:2022-03-01

    Applicant: Stratio, Inc.

    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

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