公开(公告)号：US08130028B2

公开(公告)日：2012-03-06

申请号：US12691937

申请日：2010-01-22

申请人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

发明人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

IPC分类号： G05F3/02

CPC分类号： H02M3/07

摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

摘要翻译： 提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。 在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

公开(公告)号：US20100207684A1

公开(公告)日：2010-08-19

申请号：US12691937

申请日：2010-01-22

申请人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

发明人： Su-Jin Park ,  Joung-Yeal Kim ,  Bai-Sun Kong ,  Young-Hyun Jun

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

摘要翻译： 提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。 在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

公开(公告)号：US07724073B2

公开(公告)日：2010-05-25

申请号：US12287620

申请日：2008-10-10

申请人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

发明人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

IPC分类号： G05F3/02

CPC分类号： G11C5/145

摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.

摘要翻译： 电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。 升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。 第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。 第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。 第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

公开(公告)号：US20090134937A1

公开(公告)日：2009-05-28

申请号：US12287620

申请日：2008-10-10

申请人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

发明人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

IPC分类号： G05F1/10

CPC分类号： G11C5/145

摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.

摘要翻译： 电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。 升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。 第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。 第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。 第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

公开(公告)号：US20110246857A1

公开(公告)日：2011-10-06

申请号：US13078364

申请日：2011-04-01

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

IPC分类号： H03M13/09 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1004 ,  H03M13/09

摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

摘要翻译： 存储器系统包括存储器控制器和存储器件。 存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组 具有来自存储器控制器的命令/地址通过第三通道。

公开(公告)号：US20080122523A1

公开(公告)日：2008-05-29

申请号：US12025442

申请日：2008-02-04

申请人： Hyoung-Ryol Hwang ,  Young-Hyun Jun

发明人： Hyoung-Ryol Hwang ,  Young-Hyun Jun

IPC分类号： G05F3/02 ,  G05F3/16

CPC分类号： G11C5/14

摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.

摘要翻译： 提供了包括该电压产生电路和半导体存储器件的电压产生电路。 电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少 四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压 高压。

公开(公告)号：US20050105315A1

公开(公告)日：2005-05-19

申请号：US10973806

申请日：2004-10-26

申请人： Ho-Geun Shin ,  Young-Hyun Jun

发明人： Ho-Geun Shin ,  Young-Hyun Jun

IPC分类号： G11C15/00 ,  G11C29/08

CPC分类号： G11C29/08 ,  G11C15/00

摘要： A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing unit. The match line state storing unit is connected to a word line and a match line of the plurality of CAM cells and has a plurality of state cells in which a logic level of stored data is changed according to a logic level of the match line. Errors in the CAM cell array are found by reading data stored in the plurality of state cells. The data stored in the plurality of state cells are matched when there are no errors in the CAM cell array.

摘要翻译： 公开了一种在内容可寻址存储器（CAM）和CAM单元阵列中发现错误的方法，CAM能够在CAM单元阵列中发现错误。 CAM包括具有多个CAM单元的CAM单元阵列和匹配线状态存储单元。 匹配线状态存储单元连接到多个CAM单元的字线和匹配线，并且具有根据匹配线的逻辑电平改变存储数据的逻辑电平的多个状态单元。 通过读取存储在多个状态单元中的数据来发现CAM单元阵列中的错误。 当CAM单元阵列中没有错误时，存储在多个状态单元中的数据是匹配的。

公开(公告)号：US20050094448A1

公开(公告)日：2005-05-05

申请号：US10972119

申请日：2004-10-21

申请人： Jong-Eon Lee ,  Young-Hyun Jun

发明人： Jong-Eon Lee ,  Young-Hyun Jun

IPC分类号： G11C7/00 ,  G11C29/50

CPC分类号： G11C29/50012 ,  G11C29/50

摘要： An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The test device receives the data signal in response to a reference signal, and outputs the inputted data signal as a setup and hold determining circuit. One of the reference signal and the data signal is a multiphase signal synchronized with the external clock signal. The setup and hold measuring circuit detects whether the output of the test device indicates a valid value of the data signal, and generates the detected result to the external as a setup/hold timing margin through at least one pad.

摘要翻译： 本文公开的集成电路装置包括测试装置和建立和保持测量电路。 建立和保持测量电路在测试操作模式下响应外部时钟信号产生参考信号和数据信号。 测试装置响应于参考信号接收数据信号，并输出输入的数据信号作为建立和保持确定电路。 参考信号和数据信号之一是与外部时钟信号同步的多相信号。 建立和保持测量电路检测测试装置的输出是否指示数据信号的有效值，并通过至少一个焊盘将检测结果作为建立/保持定时裕度产生到外部。

公开(公告)号：US06154079A

公开(公告)日：2000-11-28

申请号：US177818

申请日：1998-10-23

申请人： Jae-Goo Lee ,  Young-Hyun Jun

发明人： Jae-Goo Lee ,  Young-Hyun Jun

IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/13 ,  H03K5/14

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/131

摘要： A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.

摘要翻译： 负延迟电路（NDC）具有以高频率操作的NDC阵列。 该电路根据低频区域中的锁定失败信号，在NDC阵列的输入级上改变多个单位延迟级。 NDC可以在宽频带中进行负延迟操作，即使在NDC阵列中的多个级数较小时也是如此。 本发明减小了芯片的尺寸，并且由于NDC阵列具有小于一个时钟的延迟值，因此通过防止在后部的一个阶段中的锁定再次发生而减少不必要的电流消耗。

公开(公告)号：US5966337A

公开(公告)日：1999-10-12

申请号：US958932

申请日：1997-10-28

申请人： Jae-Goo Lee ,  Young-Hyun Jun

发明人： Jae-Goo Lee ,  Young-Hyun Jun

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C7/065

摘要： A bit line sense amplifier overdriving method includes a step for reaching a bit line data signal to a full swing level by driving the sense amplifiers in accordance with an overdriving voltage in an overdriving pulse interval, when an overdriving pulse signal is generated at points in which the sense amplifiers are enabled and disabled in a data read operation and a data write operation. The method maintains a sufficiently long refresh interval during a refresh operation.

摘要翻译： 位线检测放大器过驱动方法包括通过在过驱动脉冲间隔中根据过驱动电压驱动读出放大器来将位线数据信号达到全摆幅电平的步骤，当在其中产生过驱动脉冲信号时， 在数据读取操作和数据写入操作中启用和禁用读出放大器。 该方法在刷新操作期间保持足够长的刷新间隔。