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公开(公告)号：US20060036834A1
公开(公告)日：2006-02-16
申请号：US10917582
申请日：2004-08-13
申请人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
发明人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/325
摘要： A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.
摘要翻译： 一种跟踪管理架构，可以在一个或多个重复轨迹中重新使用uops。 更具体地，本发明的实施例涉及通过重复使用在微处理器的操作期间重复的迹线或迹线序列来防止对跟踪管理架构内的各种功能单元的多次访问的技术，从而避免由于多个跟踪而导致的性能差距 高速缓存访问并增加可以在处理器内执行uop的速率。
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2.发明授权Preventing a read of a next sequential chunk in branch prediction of a subject chunk 失效防止对主体块的分支预测中的下一个顺序块的读取公开(公告)号：US07174444B2
公开(公告)日：2007-02-06
申请号：US10402145
申请日：2003-03-31
申请人： Eran Altshuler , Oded Lempel , Robert Valentine , Nicolas Kacevas
发明人： Eran Altshuler , Oded Lempel , Robert Valentine , Nicolas Kacevas
IPC分类号： G06F9/30
CPC分类号： G06F9/3844
摘要： A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.
摘要翻译： 一种处理器中早期分支预测的系统和方法，通常在进行全分支预测之前评估分支目标缓冲器中的方式，以确定所述方法中的任何一种是否对应于有效的无条件分支，并且在这种确定时，生成 一个防止读取下一个连续块的信号。
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公开(公告)号：US06646647B1
公开(公告)日：2003-11-11
申请号：US09672453
申请日：2000-09-29
IPC分类号： G09G536
CPC分类号： G09G5/395 , G09G5/363 , G09G2360/121 , G09G2360/122
摘要： Embodiments of the present invention relate to displaying images from memory. A plurality of pixel attributes are retrieved from memory in a single memory transaction. At least one attribute corresponds to one scan line of a display and another attribute corresponds to another scan line of the display. A portion of one scan line using the corresponding pixel attribute is displayed. The pixel attributes corresponding to another scan line is stored in a buffer.
摘要翻译： 本发明的实施例涉及从存储器显示图像。 在单个存储器事务中从存储器检索多个像素属性。 至少一个属性对应于显示器的一个扫描线，另一个属性对应于显示器的另一个扫描线。 显示使用相应像素属性的一条扫描线的一部分。 与另一扫描线对应的像素属性存储在缓冲器中。
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公开(公告)号：US10474463B2
公开(公告)日：2019-11-12
申请号：US13997006
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
摘要： An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.
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公开(公告)号：US10209986B2
公开(公告)日：2019-02-19
申请号：US13976792
申请日：2011-12-22
申请人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
发明人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
IPC分类号： G06F9/30
摘要： A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
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公开(公告)号：US10162639B2
公开(公告)日：2018-12-25
申请号：US15912498
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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公开(公告)号：US10162638B2
公开(公告)日：2018-12-25
申请号：US15912486
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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公开(公告)号：US10162637B2
公开(公告)日：2018-12-25
申请号：US15912468
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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公开(公告)号：US10095516B2
公开(公告)日：2018-10-09
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
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公开(公告)号：US09898283B2
公开(公告)日：2018-02-20
申请号：US13976580
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
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