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    MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR HIGH RELIABILITY MEMORY DEVICES
    1.
    发明申请
    MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR HIGH RELIABILITY MEMORY DEVICES 有权
    用于高可靠性存储器件的存储器控​​制器器件，系统和方法

    公开(公告)号：US20140006730A1

    公开(公告)日：2014-01-02

    申请号：US13537877

    申请日：2012-06-29

    申请人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

    发明人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

    IPC分类号： G06F12/00

    CPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/1668 ,  G06F13/1673 ,  G06F13/1694

    摘要： A device can include a controller interface having at least one controller data output configured to output read data, and at least one controller data input configured to receive write data; and a memory device interface having a write data output configured to transmit the write data on rising and falling edges of a periodic signal, and a read data input configured to receive the read data at a same transmission rate as the write data.

    摘要翻译： 设备可以包括控制器接口，其具有被配置为输出读取数据的至少一个控制器数据输出，以及被配置为接收写入数据的至少一个控制器数据输入; 以及存储器件接口，其具有被配置为在周期信号的上升沿和下降沿发送写入数据的写入数据输出，以及被配置为以与写入数据相同的传输速率接收读取的数据的读取数据输入。

    Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices
    2.
    发明授权
    Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices 有权
    存储器控制器设备，用于在第一和第二格式之间转换用于高可靠性存储器件的存储器请求的方法

    公开(公告)号：US09304953B2

    公开(公告)日：2016-04-05

    申请号：US13537877

    申请日：2012-06-29

    申请人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

    发明人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  Karthik Navalpakam

    IPC分类号： G06F12/00 ,  G06F13/16

    CPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/1668 ,  G06F13/1673 ,  G06F13/1694

    摘要： A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.

    摘要翻译： 一种设备可以包括接口电路，其被配置为将接口电路的控制器接口处的存储器访问请求转换为与控制器接口不同的接口电路的存储器设备接口处的信号，该接口电路包括写入缓冲存储器， 存储在控制器接口的写入输入处接收到的预定数量的数据值;以及读缓冲存储器，被配置为镜像存储在写缓冲存储器中的预定数量的数据值; 其中所述存储器设备接口包括被配置为发送地址值的地址输出，被配置为在周期性信号的上升沿和下降沿发送写入数据的写入数据输出，以及被配置为以与所述周期性信号相同的速率接收读取数据的读取数据输入 写数据

    High reliability non-volatile static random access memory devices, methods and systems
    3.
    发明授权
    High reliability non-volatile static random access memory devices, methods and systems 有权
    高可靠性非易失性静态随机存取存储器件，方法与系统

    公开(公告)号：US08861271B1

    公开(公告)日：2014-10-14

    申请号：US13536661

    申请日：2012-06-28

    申请人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  David Still

    发明人： Suhail Zain ,  Helmut Puchner ,  Walt Anderson ,  David Still

    IPC分类号： G11C16/04

    CPC分类号： G11C11/41 ,  G06F17/5068 ,  G11C7/02 ,  G11C8/20 ,  G11C14/00 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

    摘要： A device can include a plurality of memory cells, each memory cell including at least one latch circuit coupled between two data nodes, a first nonvolatile section coupled to a first data node, and a second nonvolatile section coupled to a second data node; and each nonvolatile section including at least one switch element in series with a programmable nonvolatile element, the switch element configured to couple the nonvolatile element to the corresponding data node during a high reliability read operation of the memory cell.

    摘要翻译： 设备可以包括多个存储器单元，每个存储器单元包括耦合在两个数据节点之间的至少一个锁存电路，耦合到第一数据节点的第一非易失性部分和耦合到第二数据节点的第二非易失性部分; 并且每个非易失性部分包括与可编程非易失性元件串联的至少一个开关元件，所述开关元件被配置为在所述存储器单元的高可靠性读取操作期间将所述非易失性元件耦合到相应的数据节点。