公开(公告)号：US07446000B2

公开(公告)日：2008-11-04

申请号：US11826714

申请日：2007-07-18

申请人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

发明人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

摘要： A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

摘要翻译： 可以提供制造包括具有不同厚度的栅极电介质的半导体器件的方法。 制造半导体器件的方法可以包括提供具有较高电压器件区域和较低电压器件区域的衬底，在衬底上形成抗氧化层，并选择性地去除衬底上的抗氧化层的部分。 该方法还可以包括在衬底上进行第一热氧化以在抗氧化层的选择性去除的部分上形成场氧化物层，去除设置在较高电压器件区上的抗氧化层，进行第二热氧化 在所述衬底上形成在所述较高电压器件区域上的中央较高电压栅极氧化物层，去除设置在所述较低电压器件区域上的所述抗氧化层，并在所述衬底上进行第三热氧化以形成低电压栅极氧化物层 在较低电压器件区域。

公开(公告)号：US20080124873A1

公开(公告)日：2008-05-29

申请号：US11826714

申请日：2007-07-18

申请人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

发明人： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

IPC分类号： H01L21/8236

CPC分类号： H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

摘要： A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

公开(公告)号：US08050091B2

公开(公告)日：2011-11-01

申请号：US12542787

申请日：2009-08-18

申请人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

发明人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

IPC分类号： G11C16/04

CPC分类号： H01L27/11558 ,  H01L27/115 ,  H01L27/11521

摘要： An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

摘要翻译： 提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

公开(公告)号：US20070145459A1

公开(公告)日：2007-06-28

申请号：US11643837

申请日：2006-12-22

申请人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

发明人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/11558 ,  H01L27/115 ,  H01L27/11521

摘要： In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

摘要翻译： 在一个方面，提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

公开(公告)号：US07593261B2

公开(公告)日：2009-09-22

申请号：US11643837

申请日：2006-12-22

申请人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

发明人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

IPC分类号： G11C11/03

CPC分类号： H01L27/11558 ,  H01L27/115 ,  H01L27/11521

摘要： An electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

摘要翻译： 提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

公开(公告)号：US20070145467A1

公开(公告)日：2007-06-28

申请号：US11538239

申请日：2006-10-03

申请人： Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

发明人： Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L29/66825

摘要： An EEPROM includes a semiconductor substrate and a device isolation region defining first, second and third active regions in the semiconductor substrate. The EEPROM also includes at least one first insulation region in at least one first trench in the first active region. A floating gate insulation layer is disposed on the at least one first insulation region and the first, second and third active regions and a floating gate conduction layer is disposed on the floating gate insulation layer. Impurity-containing regions may be disposed in each of the first, second and third active regions at respective sides of the floating gate conduction layer. The floating gate insulation layer may include at least one thinned portion proximate the at least one first insulation region, which may aid Fowler-Nordheim tunneling at this site.

摘要翻译： EEPROM包括半导体衬底和限定半导体衬底中的第一，第二和第三有源区的器件隔离区。 EEPROM还包括在第一有源区域中的至少一个第一沟槽中的至少一个第一绝缘区域。 浮置栅极绝缘层设置在至少一个第一绝缘区域和第一，第二和第三有源区域上，并且浮置栅极导电层设置在浮置栅极绝缘层上。 含杂质的区域可以布置在浮置栅极导电层的相应侧的第一，第二和第三有源区域的每一个中。 浮栅绝缘层可以包括靠近至少一个第一绝缘区域的至少一个变薄部分，这可以有助于在该部位的Fowler-Nordheim隧道。

公开(公告)号：US20070148851A1

公开(公告)日：2007-06-28

申请号：US11608529

申请日：2006-12-08

申请人： Myung-hee Kim ,  Geun-sook Park ,  Sang-bae Yi ,  Ho-ik Hwang ,  Hye-young Park

发明人： Myung-hee Kim ,  Geun-sook Park ,  Sang-bae Yi ,  Ho-ik Hwang ,  Hye-young Park

IPC分类号： H01L21/8238

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A method of programming an EEPROM including a first active region, a second active region and a third active region located separately in a semiconductor substrate, a common floating gate above and intersecting the active regions, first impurity regions located at both sides of the common floating gate in the first active region, second impurity regions located at both sides of the common floating gate in the second active regions and third impurity region, located at both sides of the common floating gate in the third active region. The method includes: applying a programming voltage to the first impurity regions in the first active region and the third impurity regions in the third active region; and applying a ground voltage to the second impurity regions in the second active region.

摘要翻译： 一种编程EEPROM的方法，包括分别位于半导体衬底中的第一有源区，第二有源区和第三有源区，位于有源区之上并与有源区相交的公共浮栅，位于公共浮置的两侧的第一杂质区 位于第一有源区中的栅极，位于第二有源区域中的公共浮置栅极两侧的第二杂质区域和位于第三有源区域中的公共浮置栅极两侧的第三杂质区域。 该方法包括：对第一有源区中的第一杂质区和第三有源区中的第三杂质区施加编程电压; 以及对第二有源区中的第二杂质区施加接地电压。