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    EEPROM devices and methods of operating and fabricating the same
    4.
    发明申请
    EEPROM devices and methods of operating and fabricating the same 失效
    EEPROM器件及其操作和制造方法

    公开(公告)号：US20070145459A1

    公开(公告)日：2007-06-28

    申请号：US11643837

    申请日：2006-12-22

    申请人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

    发明人： Geun-sook Park ,  Sang-bae Yi ,  Soo-cheol Lee ,  Ho-ik Hwang ,  Tae-jung Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11558 ,  H01L27/115 ,  H01L27/11521

    摘要： In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite sides of the floating gate, a first interconnect connected to the first active region, a second interconnect connected to the second active region, and a third interconnect connected to either one of the source/drain regions.

    摘要翻译： 在一个方面，提供电可擦除和可编程只读存储器（EEPROM）。 EEPROM包括半导体衬底，其包括间隔开的第一，第二和第三有源区域，跨越第一至第三有源区域的公共浮动栅极，形成在浮置栅极的相对侧上的第三有源区域中的源极/漏极区域，第一 连接到第一有源区的互连，连接到第二有源区的第二互连以及连接到源/漏区中的任一个的第三互连。

    Source driver for controlling a slew rate and a method for controlling the slew rate
    7.
    发明申请
    Source driver for controlling a slew rate and a method for controlling the slew rate 有权
    用于控制转换速率的源驱动器和控制转换速率的方法

    公开(公告)号：US20070008009A1

    公开(公告)日：2007-01-11

    申请号：US11445805

    申请日：2006-06-03

    申请人： Kyoung-Mok Son ,  Soo-Cheol Lee

    发明人： Kyoung-Mok Son ,  Soo-Cheol Lee

    IPC分类号： H03K19/094

    CPC分类号： H03K17/165 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0291

    摘要： A source driver for controlling a slew rate of a liquid crystal display (LCD) and a method for controlling the slew rate is provided. The source driver includes a plurality of output buffers for driving data lines, and a bias circuit for varying a bias voltage inputted to the output buffers to control a slew rate of the output buffers.

    摘要翻译： 提供了用于控制液晶显示器（LCD）的转换速率的源极驱动器和用于控制压摆率的方法。 源极驱动器包括用于驱动数据线的多个输出缓冲器和用于改变输入到输出缓冲器的偏置电压以控制输出缓冲器的转换速率的偏置电路。

    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs
    8.
    发明授权
    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs 有权
    SOI半导体集成电路，用于消除SOI MOSFET中的浮体效应

    公开(公告)号：US06573563B2

    公开(公告)日：2003-06-03

    申请号：US09872429

    申请日：2001-06-01

    申请人： Soo-Cheol Lee ,  Tae-Jung Lee

    发明人： Soo-Cheol Lee ,  Tae-Jung Lee

    IPC分类号： H01L2701

    CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/78615 ,  H01L29/78621

    摘要： A silicon-on-insulator (SOI) integrated, circuit is provided. A plurality of transistor active regions and at least one body contact active region are formed on an SOI substrate. A semiconductor residue layer, which is thinner than the transistor active regions and the body contact active region, is disposed between the transistor active regions and the body contact active region. The transistor active regions, the body contact active region and the semiconductor residue layer are disposed on a buried insulating layer of the SOI substrate. The semiconductor residue layer is covered with a partial trench isolation layer. A bar-shaped full trench isolation layer is interposed between the adjacent transistor active regions. The full trench isolation layer is in contact with sidewalls of the transistor active regions adjacent thereto and is in contact with the buried insulating layer between the adjacent transistor active regions. An insulated gate pattern crosses over the respective transistor active regions. The insulated gate pattern is disposed to be parallel with the full trench isolation layer.

    摘要翻译： 提供了绝缘体上硅（SOI）集成电路。 在SOI衬底上形成多个晶体管有源区和至少一个体接触有源区。 比晶体管有源区域和体接触有源区域薄的半导体残留层设置在晶体管有源区域和体接触有源区域之间。 晶体管有源区，体接触有源区和半导体残留层设置在SOI衬底的掩埋绝缘层上。 半导体残渣层被部分沟槽隔离层覆盖。 在相邻的晶体管有源区域之间插入条形全沟槽隔离层。 全沟槽隔离层与与其相邻的晶体管有源区的侧壁接触并与相邻的晶体管有源区之间的掩埋绝缘层接触。 绝缘栅极图案跨过相应的晶体管有源区。 绝缘栅极图案设置成与全沟槽隔离层平行。

    MOS transistor for high-speed and high-performance operation and manufacturing method thereof
    10.
    发明授权
    MOS transistor for high-speed and high-performance operation and manufacturing method thereof 有权
    MOS晶体管用于高速和高性能的操作及制造方法

    公开(公告)号：US06274906B1

    公开(公告)日：2001-08-14

    申请号：US09198230

    申请日：1998-11-23

    申请人： Hyun-Sik Kim ,  Heon-Jong Shin ,  Soo-Cheol Lee

    发明人： Hyun-Sik Kim ,  Heon-Jong Shin ,  Soo-Cheol Lee

    IPC分类号： H01L2976

    CPC分类号： H01L29/6659 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

    摘要： A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and an oxide layer formed by surface oxidation of the gate electrodes. A first spacer is formed on the side wall of the gate electrodes, and a second spacer is formed on the inclined side wall. A first impurity layer of low concentration is formed at a first depth by a second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate to be self-aligned at the edge of the gate electrode. A second impurity layer of middle concentration is formed at a deeper second depth than the first depth by the second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate. A third impurity layer having higher impurity concentration than that of the semiconductor, is formed at a third depth for surrounding the second impurity layer of middle concentration by a first conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate to be self-aligned at the edge of the first spacer. A fourth impurity layer of high concentration formed at a fourth depth deeper than the third depth by the second conductivity type impurity implanted in the vicinity of the surface of the semiconductor substrate to be aligned at the edge of the second spacer.

    摘要翻译： 本发明的MOS晶体管包括第一导电型杂质的半导体衬底，形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上的栅电极和通过栅电极的表面氧化形成的氧化物层。 第一间隔件形成在栅电极的侧壁上，第二间隔件形成在倾斜侧壁上。 通过注入在半导体衬底的表面附近的第二导电类型的杂质在第一深度处形成低浓度的第一杂质层，以在栅电极的边缘处自对准。 通过注入在半导体衬底的表面附近的第二导电类型杂质，在比第一深度更深的第二深度处形成中等浓度的第二杂质层。 在第三深度形成第三杂质层，该第三杂质层通过注入在半导体衬底的表面附近的第一导电型杂质包围中间浓度的第二杂质层以进行自对准 在第一间隔物的边缘。 通过注入在半导体衬底的表面附近的第二导电类型杂质在第二深度上比第三深度更深的第四深度形成第四杂质层，以在第二间隔物的边缘对齐。