公开(公告)号：US20140141537A1

公开(公告)日：2014-05-22

申请号：US14084212

申请日：2013-11-19

Applicant: SunEdison, Inc.

Inventor： Robert J. Falster ,  Vladimir V. Voronkov ,  Marco Cornara ,  Daniela Gambaro ,  Massimiliano Olmo

IPC: H01L21/324 ,  H01L21/66

CPC classification number: H01L21/324 ,  C30B29/06 ,  C30B33/02 ,  H01L22/12

Abstract: Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour.

Abstract translation: 用于处理硅晶片以形成高密度不均匀分布的氧的方法在其中析出核，使得在经受基本上任意的任何电子器件制造工艺的热处理循环后，晶片在本体中形成氧沉淀物， 公开了表面附近的无沉淀区。 所述方法包括通过在约400℃至约600℃之间进行热处理至少约1小时来活化无活性氧沉淀核。

公开(公告)号：US20150123248A1

公开(公告)日：2015-05-07

申请号：US14596269

申请日：2015-01-14

Applicant: SunEdison Inc.

Inventor： Robert J. Falster ,  Vladimir Voronkov

IPC: H01L29/16 ,  H01L21/322

CPC classification number: H01L29/16 ,  H01L21/3221 ,  H01L31/1804 ,  H01L31/1864 ,  Y02E10/547 ,  Y02P70/521

Abstract: Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.

Abstract translation: 公开了抑制硅晶片中的少数载流子寿命劣化的方法。 该方法包括骤冷冷却晶片以增加硅晶片中的纳米沉淀物的密度以及间隙原子被纳米沉淀物消耗的速率。

公开(公告)号：US20140187022A1

公开(公告)日：2014-07-03

申请号：US14142553

申请日：2013-12-27

Applicant: SunEdison, Inc.

Inventor： Robert J. Falster ,  Vladimir V. Voronkov ,  John A. Pitney ,  Peter D. Albrecht

IPC: H01L21/322 ,  H01L21/302

CPC classification number: H01L21/322 ,  C30B25/12 ,  H01L21/302 ,  H01L21/68735 ,  H01L21/6875

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract translation: 公开了用于制备具有减小的应变的异质结构的装置和方法。 异质结构可以包括符合具有与结构不同的晶格的表面层的半导体结构，以形成相对低缺陷的异质结构。

公开(公告)号：US20140182788A1

公开(公告)日：2014-07-03

申请号：US14142559

申请日：2013-12-27

Applicant: SunEdison, Inc.

Inventor： Robert J. Falster ,  Vladimir V. Voronkov ,  John A. Pitney ,  Peter D. Albrecht

IPC: H01L21/67

CPC classification number: H01L21/322 ,  C30B25/12 ,  H01L21/302 ,  H01L21/67092 ,  H01L21/6838 ,  H01L21/68735 ,  H01L21/6875

Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Abstract translation: 用于制备具有降低的缺陷浓度的异质结构的装置，包括用于对半导体衬底施加应力以使其符合具有不同晶格常数的晶体的装置。

公开(公告)号：US20140187023A1

公开(公告)日：2014-07-03

申请号：US14142556

申请日：2013-12-27

Applicant: SunEdison, Inc.

Inventor： Robert J. Falster ,  Vladimir V. Voronkov ,  John A. Pitney ,  Peter D. Albrecht

IPC: H01L21/322

CPC classification number: H01L21/322 ,  C30B25/12 ,  H01L21/302 ,  H01L21/68735 ,  H01L21/6875

Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Abstract translation: 公开了用于制备具有减小的应变的异质结构的装置和方法。 异质结构可以包括符合具有与结构不同的晶格的表面层的半导体结构，以形成相对低缺陷的异质结构。

公开(公告)号：US09142616B2

公开(公告)日：2015-09-22

申请号：US14596269

申请日：2015-01-14

Applicant: SunEdison Inc.

Inventor： Robert J. Falster ,  Vladimir Voronkov

IPC: H01L21/324 ,  H01L29/16 ,  H01L21/322

CPC classification number: H01L29/16 ,  H01L21/3221 ,  H01L31/1804 ,  H01L31/1864 ,  Y02E10/547 ,  Y02P70/521

Abstract: Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.

Abstract translation: 公开了抑制硅晶片中的少数载流子寿命劣化的方法。 该方法包括骤冷冷却晶片以增加硅晶片中的纳米沉淀物的密度以及间隙原子被纳米沉淀物消耗的速率。