公开(公告)号：US08760958B2

公开(公告)日：2014-06-24

申请号：US13421704

申请日：2012-03-15

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC分类号： G11C8/00 ,  G11C8/16

CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

摘要翻译： 为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。 单端读取允许内存系统同时处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 位单元格。 因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。 可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

公开(公告)号：US08433880B2

公开(公告)日：2013-04-30

申请号：US12584645

申请日：2009-09-08

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/00

CPC分类号： G06F12/0292 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/657

摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

摘要翻译： 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。

公开(公告)号：US08589851B2

公开(公告)日：2013-11-19

申请号：US12806946

申请日：2010-08-23

申请人： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F3/0607 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/0844 ,  G06F12/0851 ,  G06F12/0855

摘要： Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

摘要翻译： 为集成电路设计存储器子系统可能是耗时且昂贵的任务。 为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。 自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。 潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。 满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。 当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及存储器系统的测试套件。

公开(公告)号：US20130242677A1

公开(公告)日：2013-09-19

申请号：US13421704

申请日：2012-03-15

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC分类号： G11C8/16 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

摘要： To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

摘要翻译： 为了处理多个并发存储器请求，提出了一个双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问位单元的真实侧和假侧。 单端读取允许内存系统同时处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 位单元格。 因此，具有电压辅助的单端操作允许存储器系统处理两个并行写入操作。 可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

公开(公告)号：US08504796B2

公开(公告)日：2013-08-06

申请号：US13570125

申请日：2012-08-08

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F13/00

CPC分类号： G06F12/1009 ,  G06F12/06 ,  G06F12/0851 ,  G06F12/10 ,  G11C7/1075

摘要： A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. A changeable mapping table that maps the virtualized memory addresses to physical memory addresses is stored in the same memory system.

摘要翻译： 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。 将虚拟内存地址映射到物理内存地址的可更改映射表存储在同一个内存系统中。

公开(公告)号：US20110145513A1

公开(公告)日：2011-06-16

申请号：US12928698

申请日：2010-12-15

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/08

CPC分类号： G06F12/0844 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/10

摘要： A reduced latency memory system that prevents memory bank conflicts. The reduced latency memory system receives a read request and write request. The read request is then handled by simultaneously fetching data from a main memory and a cache memory. The address of the read request is compared with a cache tag value and if the cache tag value matches the address of the read request, the data from the cache memory is served. The write request is stored and handled in a subsequent memory cycle.

摘要翻译： 减少延迟的存储器系统，防止存储器冲突。 减少延迟的存储器系统接收读请求和写请求。 然后通过从主存储器和高速缓冲存储器同时提取数据来处理读请求。 将读取请求的地址与缓存标签值进行比较，并且如果高速缓存标签值与读取请求的地址匹配，则来自高速缓冲存储器的数据被提供。 写请求在随后的存储器周期中被存储和处理。

公开(公告)号：US09442846B2

公开(公告)日：2016-09-13

申请号：US12806631

申请日：2010-08-17

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0673 ,  G06F12/08 ,  G06F2212/254

摘要： A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

摘要翻译： 公开了一种用于设计和构造分层存储器系统的系统和方法。 公开了多种不同的算法存储器块。 每个算法存储器块包括实现特定存储算法和一组较低级存储器组件的存储器控​​制器。 这些较低级存储器组件中的每一个可以用另一个算法存储器块或基本存储器块来构造。 通过在各种不同的分层组织中组织算法存储器块，可以创建提供新特征的不同复杂的存储器系统。

公开(公告)号：US09293187B2

公开(公告)日：2016-03-22

申请号：US13245426

申请日：2011-09-26

申请人： Sundar Iyer ,  Shang-Tse Chuang

发明人： Sundar Iyer ,  Shang-Tse Chuang

IPC分类号： G06F12/06 ,  G11C11/406

CPC分类号： G11C11/40603 ,  G11C11/40618

摘要： Dynamic memory systems require each memory cell to be continually refreshed. During a memory refresh operation, the refreshed memory cells cannot be accessed by a memory read or write operation. In multi-bank dynamic memory systems, concurrent refresh systems allow memory refresh circuitry to refresh memory banks that are not currently involved in memory access operations. To efficiently refresh memory banks and advanced round robin refresh system refreshes memory banks in a nominal round robin manner but skips memory banks blocked by memory access operations. Skipped memory banks are prioritized and then refreshed when they are no longer blocked.

摘要翻译： 动态存储器系统要求每个存储单元被不断刷新。 在存储器刷新操作期间，刷新的存储器单元不能被存储器读或写操作访问。 在多行动态存储器系统中，并发刷新系统允许存储器刷新电路来刷新当前不参与存储器存取操作的存储器组。 为了有效地刷新内存库和高级循环刷新系统，以一种名义上的循环方式刷新内存库，但是忽略了内存访问操作阻塞的内存块。 跳过的内存库被优先排列，然后在不再被阻止时刷新。

公开(公告)号：US09058860B2

公开(公告)日：2015-06-16

申请号：US13434296

申请日：2012-03-29

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C8/16 ,  G11C11/413

CPC分类号： G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

摘要： Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

摘要翻译： 现代数字集成电路中通常需要多端口存储器电路来存储数据。 多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。 多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。 然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。 公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

公开(公告)号：US08902672B2

公开(公告)日：2014-12-02

申请号：US13732372

申请日：2013-01-01

申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian ,  Kartik Mohanram

发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian ,  Kartik Mohanram

IPC分类号： G11C8/16 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C11/419 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C11/412

摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.

摘要翻译： 大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。 为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。 可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。 为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。