公开(公告)号：US20130049095A1

公开(公告)日：2013-02-28

申请号：US13599680

申请日：2012-08-30

申请人： Sung Jin WHANG ,  Dong Sun SHEEN ,  Seung Ho PYI ,  Min Soo KIM

发明人： Sung Jin WHANG ,  Dong Sun SHEEN ,  Seung Ho PYI ,  Min Soo KIM

IPC分类号： H01L29/788 ,  H01L21/20

CPC分类号： H01L27/11556 ,  H01L29/7889

摘要： A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.

摘要翻译： 根据本发明的实施例的半导体器件包括从半导体衬底向上突出的垂直沟道层，覆盖垂直沟道层的侧壁的隧道绝缘层，彼此分离并堆叠的多个浮动栅极 沿着垂直沟道层，并且在其间插入隧道绝缘层的周围的垂直沟道层，分别包围多个浮置栅极的多个控制栅极和设置在多个控制栅极之间的层间绝缘层。

公开(公告)号：US20130320424A1

公开(公告)日：2013-12-05

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，第二源极层基本上形成在第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US20140015057A1

公开(公告)日：2014-01-16

申请号：US13599148

申请日：2012-08-30

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Sung Ik MOON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Sung Ik MOON

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L21/0332 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

摘要： A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.

摘要翻译： 半导体器件包括单元结构; n个第一衬垫结构，形成在单元结构的一侧，并且每个构造成具有其中2n层形成一个阶段的阶梯形式; 以及形成在所述电池结构的另一侧上的n个第二焊盘结构，每个被配置为具有其中2n层形成一个级的阶梯形式，其中n是1或更高的自然数，并且所述第一焊盘结构和所述第二焊盘结构 具有不同高度的不对称步骤形式。

公开(公告)号：US20130207182A1

公开(公告)日：2013-08-15

申请号：US13600190

申请日：2012-08-30

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Jin Ho BIN

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Jin Ho BIN

IPC分类号： H01L21/20 ,  H01L29/78

CPC分类号： H01L27/11582

摘要： A semiconductor device includes vertical channel layers, a pipe channel layer coupling bottoms of the vertical channel layers, a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer, and a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer.

摘要翻译： 半导体器件包括垂直沟道层，连接垂直沟道层的底部的管道沟道层，与底部表面接触的管道和管道沟道层的侧表面，以及由非导电材料形成的虚拟管栅极和接触 管道通道层的顶表面。

公开(公告)号：US20130193503A1

公开(公告)日：2013-08-01

申请号：US13602038

申请日：2012-08-31

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Hyun Soo SHON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Hyun Soo SHON

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L27/11573

摘要： A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

公开(公告)号：US20130153978A1

公开(公告)日：2013-06-20

申请号：US13598528

申请日：2012-08-29

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

公开(公告)号：US20130009229A1

公开(公告)日：2013-01-10

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Jung Yun CHANG

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Jung Yun CHANG

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

摘要翻译： 半导体器件包括各自被配置为包括一对通道的存储器块，每个通道包括形成在存储器块的管道中的管道通道和与管道通道耦合的漏极侧通道和源极通道; 位于与其他存储块相邻的存储块之间的第一狭缝; 以及设置在每对通道的源极侧通道和漏极侧通道之间的第二狭缝。