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1.发明申请APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING A RACH SIGNAL IN SC-FDMA SYSTEM 审中-公开用于在SC-FDMA系统中传输和接收RACH信号的装置和方法公开(公告)号：US20130250921A1
公开(公告)日：2013-09-26
申请号：US13894973
申请日：2013-05-15
申请人： Sung Lark KWON , Dong Joo Park , Hyuck Chan Kwon , Young Kwon Ryu , Hoo Young Jeong , Hong Jik Kim , Jung Seong Lee , Jae Won Jang , Byoung Seong Park , Hee Gul Park
发明人： Sung Lark KWON , Dong Joo Park , Hyuck Chan Kwon , Young Kwon Ryu , Hoo Young Jeong , Hong Jik Kim , Jung Seong Lee , Jae Won Jang , Byoung Seong Park , Hee Gul Park
IPC分类号： H04W72/08
CPC分类号： H04W72/082 , H04J13/0059 , H04L5/0005 , H04L5/0007 , H04L5/0037 , H04L5/023 , H04L27/2613 , H04L27/2626 , H04L27/2655
摘要： Embodiments of the present invention may provide an apparatus and a method for transmitting and receiving a random access channel (RACH) in a single carrier-frequency division multiple access (SC-FDMA) system. A frequency domain RACH signal may be mapped to a localized sub-frequency band of an entire frequency band available to the SC-FDMA system. A guard band including at least one sub carrier may be allocated between the RACH signal band and other channel signal bands. A guard time may be allocated between the RACE signal and other channel signals in the time domain. The RACH signal may include a short message including information related to a mobile station. The RACE signal may be detected in a frequency based method, a time based method or a sliding matched filter based method. Receiver complexity can be decreased if the RACH signal includes a CAZAC code sequence for a preamble. In such a case, a receive delay may be simply calculated and then adjusted more accurately.
摘要翻译： 本发明的实施例可以提供在单载波频分多址（SC-FDMA）系统中发送和接收随机接入信道（RACH）的装置和方法。 频域RACH信号可以映射到SC-FDMA系统可用的整个频带的本地化子频带。 可以在RACH信号频带和其它信道信号频带之间分配包括至少一个子载波的保护频带。 可以在RACE信号和时域中的其他信道信号之间分配保护时间。 RACH信号可以包括包括与移动台有关的信息的短消息。 可以以基于频率的方法，基于时间的方法或基于滑动匹配滤波器的方法来检测RACE信号。 如果RACH信号包括用于前同步码的CAZAC码序列，则接收机复杂度可以降低。 在这种情况下，可以简单地计算接收延迟，然后更精确地进行调整。
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2.发明申请Apparatus and method for transmitting and receiving a RACH signal in SC-FDMA system 有权用于在SC-FDMA系统中发送和接收RACH信号的装置和方法公开(公告)号：US20070171889A1
公开(公告)日：2007-07-26
申请号：US11654000
申请日：2007-01-17
申请人： Sung Lark Kwon , Dong Joo Park , Hyuck Chan Kwon , Young Kwon Ryu , Hoo Young Jeong , Hong Jik Kim , Jung Seung Lee , Jae Won Jang , Byoung Seong Park , Hee Gul Park
发明人： Sung Lark Kwon , Dong Joo Park , Hyuck Chan Kwon , Young Kwon Ryu , Hoo Young Jeong , Hong Jik Kim , Jung Seung Lee , Jae Won Jang , Byoung Seong Park , Hee Gul Park
IPC分类号： H04J3/06
CPC分类号： H04W72/082 , H04J13/0059 , H04L5/0005 , H04L5/0007 , H04L5/0037 , H04L5/023 , H04L27/2613 , H04L27/2626 , H04L27/2655
摘要： Embodiments of the present invention may provide an apparatus and a method for transmitting and receiving a random access channel (RACH) in a single carrier-frequency division multiple access (SC-FDMA) system. A frequency domain RACH signal may be mapped to a localized sub-frequency band of an entire frequency band available to the SC-FDMA system. A guard band including at least one sub carrier may be allocated between the RACH signal band and other channel signal bands. A guard time may be allocated between the RACH signal and other channel signals in the time domain. The RACH signal may include a short message including information related to a mobile station. The RACH signal may be detected in a frequency based method, a time based method or a sliding matched filter based method. Receiver complexity can be decreased if the RACH signal includes a CAZAC code sequence for a preamble. In such a case, a receive delay may be simply calculated and then adjusted more accurately.
摘要翻译： 本发明的实施例可以提供在单载波频分多址（SC-FDMA）系统中发送和接收随机接入信道（RACH）的装置和方法。 频域RACH信号可以映射到SC-FDMA系统可用的整个频带的本地化子频带。 可以在RACH信号频带和其它信道信号频带之间分配包括至少一个子载波的保护频带。 可以在RACH信号和时域中的其它信道信号之间分配保护时间。 RACH信号可以包括包括与移动台有关的信息的短消息。 可以基于频率的方法，基于时间的方法或基于滑动匹配滤波器的方法来检测RACH信号。 如果RACH信号包括用于前同步码的CAZAC码序列，则接收机复杂度可以降低。 在这种情况下，可以简单地计算接收延迟，然后更精确地进行调整。
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3.发明授权Apparatus and method for transmitting and receiving a RACH signal in SC-FDMA system 有权用于在SC-FDMA系统中发送和接收RACH信号的装置和方法公开(公告)号：US08457076B2
公开(公告)日：2013-06-04
申请号：US11654000
申请日：2007-01-17
申请人： Sung Lark Kwon , Dong Joo Park , Hyuck Chan Kwon , Young Kwon Ryu , Hoo Young Jeong , Hong Jik Kim , Jung Seung Lee , Jae Won Jang , Byoung Seong Park , Hee Gul Park
发明人： Sung Lark Kwon , Dong Joo Park , Hyuck Chan Kwon , Young Kwon Ryu , Hoo Young Jeong , Hong Jik Kim , Jung Seung Lee , Jae Won Jang , Byoung Seong Park , Hee Gul Park
CPC分类号： H04W72/082 , H04J13/0059 , H04L5/0005 , H04L5/0007 , H04L5/0037 , H04L5/023 , H04L27/2613 , H04L27/2626 , H04L27/2655
摘要： Embodiments of the present invention may provide an apparatus and a method for transmitting and receiving a random access channel (RACH) in a single carrier-frequency division multiple access (SC-FDMA) system. A frequency domain RACH signal may be mapped to a localized sub-frequency band of an entire frequency band available to the SC-FDMA system. A guard band including at least one sub carrier may be allocated between the RACH signal band and other channel signal bands. A guard time may be allocated between the RACH signal and other channel signals in the time domain. The RACH signal may include a short message including information related to a mobile station. The RACH signal may be detected in a frequency based method, a time based method or a sliding matched filter based method. Receiver complexity can be decreased if the RACH signal includes a CAZAC code sequence for a preamble. In such a case, a receive delay may be simply calculated and then adjusted more accurately.
摘要翻译： 本发明的实施例可以提供在单载波频分多址（SC-FDMA）系统中发送和接收随机接入信道（RACH）的装置和方法。 频域RACH信号可以映射到SC-FDMA系统可用的整个频带的本地化子频带。 可以在RACH信号频带和其它信道信号频带之间分配包括至少一个子载波的保护频带。 可以在RACH信号和时域中的其它信道信号之间分配保护时间。 RACH信号可以包括包括与移动台有关的信息的短消息。 可以基于频率的方法，基于时间的方法或基于滑动匹配滤波器的方法来检测RACH信号。 如果RACH信号包括用于前同步码的CAZAC码序列，则接收机复杂度可以降低。 在这种情况下，可以简单地计算接收延迟，然后更精确地进行调整。
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公开(公告)号：US20170331664A1
公开(公告)日：2017-11-16
申请号：US15592087
申请日：2017-05-10
申请人： Hyun Soo Cheon , Hong Jik Kim , Tejas M. Bhatt
发明人： Hyun Soo Cheon , Hong Jik Kim , Tejas M. Bhatt
CPC分类号： H04L27/2678 , H04L27/2636 , H04L27/2657 , H04L27/2675
摘要： Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary embodiment, an apparatus includes a DMRS frequency offset estimator that determines a DMRS frequency offset estimate based on DMRS symbols received in an uplink transmission, and a cyclic prefix (CP) frequency offset estimator that determines a CP frequency offset estimate based on cyclic prefix values in the uplink transmission. The apparatus also includes an offset combiner that combines the DMRS frequency offset estimate with the CP frequency offset estimate to generate a final frequency offset estimate.
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5.发明申请公开(公告)号：US20170220523A1
公开(公告)日：2017-08-03
申请号：US15379207
申请日：2016-12-14
申请人： Mehran Nekuii , Hong Jik Kim
发明人： Mehran Nekuii , Hong Jik Kim
CPC分类号： G06F17/142 , H04J11/00 , H04J2211/005
摘要： Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2̂2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected from the R2, R3, and R2̂2 stages based on an FFT point size to form an FFT engine. The FFT engine receives input samples at a first stage of the sequence and generate an FFT output result that is output from a last stage of the sequence. The sequence includes no more than one R3 stage.
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公开(公告)号：US10171278B2
公开(公告)日：2019-01-01
申请号：US15592087
申请日：2017-05-10
申请人： Hyun Soo Cheon , Hong Jik Kim , Tejas M. Bhatt
发明人： Hyun Soo Cheon , Hong Jik Kim , Tejas M. Bhatt
IPC分类号： H04L27/26
摘要： Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary embodiment, an apparatus includes a DMRS frequency offset estimator that determines a DMRS frequency offset estimate based on DMRS symbols received in an uplink transmission, and a cyclic prefix (CP) frequency offset estimator that determines a CP frequency offset estimate based on cyclic prefix values in the uplink transmission. The apparatus also includes an offset combiner that combines the DMRS frequency offset estimate with the CP frequency offset estimate to generate a final frequency offset estimate.
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7.发明申请公开(公告)号：US20170192936A1
公开(公告)日：2017-07-06
申请号：US15272332
申请日：2016-09-21
申请人： Yuanbin Guo , Hong Jik Kim
发明人： Yuanbin Guo , Hong Jik Kim
CPC分类号： G06F17/141 , G06F17/142 , G06F17/16 , H04W16/18
摘要： A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix computations. The configurable mixed radix engine performs the selected radix computation on data received from the memory bank through the pipeline to generate a radix result. The apparatus also includes a controller that controls how many radix computation iterations will be performed to compute an N-point DFT/IDFT based on a radix factorization.
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公开(公告)号：US10311018B2
公开(公告)日：2019-06-04
申请号：US15292015
申请日：2016-10-12
申请人： Yuanbin Guo , Hong Jik Kim
发明人： Yuanbin Guo , Hong Jik Kim
摘要： A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.
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公开(公告)号：US20180352557A1
公开(公告)日：2018-12-06
申请号：US15594497
申请日：2017-06-02
摘要： Methods and apparatus for a unified baseband architecture. In an exemplary embodiment, an apparatus includes a shared memory having a plurality of access ports and a scheduler that outputs scheduled jobs. Each scheduled job identifies data processing to be performed. The apparatus also includes a plurality of functional elements coupled to the plurality of access ports, respectively, to access the shared memory. Each functional element is operable to retrieve selected data from the shared memory, process the selected data to generate processed data, and store the processed data into the shared memory based on a received scheduled job.
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10.发明授权公开(公告)号：US10114797B2
公开(公告)日：2018-10-30
申请号：US15272332
申请日：2016-09-21
申请人： Yuanbin Guo , Hong Jik Kim
发明人： Yuanbin Guo , Hong Jik Kim
摘要： A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix computations. The configurable mixed radix engine performs the selected radix computation on data received from the memory bank through the pipeline to generate a radix result. The apparatus also includes a controller that controls how many radix computation iterations will be performed to compute an N-point DFT/IDFT based on a radix factorization.
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