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    Nonvolatile memory devices with trenched side-wall transistors and method of fabricating the same
    3.
    发明授权
    Nonvolatile memory devices with trenched side-wall transistors and method of fabricating the same 有权
    具有沟槽侧壁晶体管的非易失性存储器件及其制造方法

    公开(公告)号：US07391071B2

    公开(公告)日：2008-06-24

    申请号：US11233857

    申请日：2005-09-23

    申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

    发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

    摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

    摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

    Nonvolatile memory devices with trenched side-wall transistors and method of fabricating the same
    4.
    发明申请
    Nonvolatile memory devices with trenched side-wall transistors and method of fabricating the same 有权
    具有沟槽侧壁晶体管的非易失性存储器件及其制造方法

    公开(公告)号：US20060063331A1

    公开(公告)日：2006-03-23

    申请号：US11233857

    申请日：2005-09-23

    申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

    发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

    IPC分类号： H01L21/336 ,  H01L21/3205

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

    摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

    摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

    Electronic devices having partially elevated source/drain structures and related methods
    5.
    发明申请
    Electronic devices having partially elevated source/drain structures and related methods 审中-公开
    具有部分升高的源极/漏极结构和相关方法的电子器件

    公开(公告)号：US20060033166A1

    公开(公告)日：2006-02-16

    申请号：US11020311

    申请日：2004-12-22

    申请人： Min-Cheol Park ,  Sung-Hoi Hur

    发明人： Min-Cheol Park ,  Sung-Hoi Hur

    IPC分类号： H01L29/94

    CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/78

    摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

    摘要翻译： 形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。 可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。 此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。 还讨论了相关设备。

    Methods of forming electronic devices having partially elevated source/drain structures
    6.
    发明授权
    Methods of forming electronic devices having partially elevated source/drain structures 失效
    形成具有部分升高的源极/漏极结构的电子器件的方法

    公开(公告)号：US07585710B2

    公开(公告)日：2009-09-08

    申请号：US11638775

    申请日：2006-12-14

    申请人： Min-Cheol Park ,  Sung-Hoi Hur

    发明人： Min-Cheol Park ,  Sung-Hoi Hur

    IPC分类号： H01L29/72

    CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/78

    摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

    摘要翻译： 形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。 可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。 此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。 还讨论了相关设备。

    Methods of forming electronic devices having partially elevated source/drain structures
    7.
    发明申请
    Methods of forming electronic devices having partially elevated source/drain structures 失效
    形成具有部分升高的源极/漏极结构的电子器件的方法

    公开(公告)号：US20070090466A1

    公开(公告)日：2007-04-26

    申请号：US11638775

    申请日：2006-12-14

    申请人： Min-Cheol Park ,  Sung-Hoi Hur

    发明人： Min-Cheol Park ,  Sung-Hoi Hur

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/78

    摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

    摘要翻译： 形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。 可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。 此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。 还讨论了相关设备。

    Apparatus and method for channel estimation for data demodulation in broadband wireless access system
    8.
    发明授权
    Apparatus and method for channel estimation for data demodulation in broadband wireless access system 有权
    宽带无线接入系统中数据解调的信道估计装置及方法

    公开(公告)号：US07801252B2

    公开(公告)日：2010-09-21

    申请号：US11710852

    申请日：2007-02-26

    申请人： Seo-Goo Lee ,  Tae-Gon Kim ,  Min-Cheol Park ,  Yun-Sang Park ,  Bong-Gee Song ,  In-Hyoung Kim

    发明人： Seo-Goo Lee ,  Tae-Gon Kim ,  Min-Cheol Park ,  Yun-Sang Park ,  Bong-Gee Song ,  In-Hyoung Kim

    IPC分类号： H03D1/00 ,  H04L27/06

    CPC分类号： H04L25/023

    摘要： Provided is a channel estimation apparatus and method. In the channel estimation apparatus, a channel estimator performs channel estimation onto a received symbol and output a channel estimation result. The channel estimation result is stored in an estimation buffer along with a channel estimation result compensated in a preamble phase compensator. The preamble phase compensator receives a channel estimation result for pilot subcarriers of a data symbol and a preamble channel estimation result from the estimation buffer, acquires a phase rotation value between them, and compensates the preamble channel estimation result with the phase rotation value. When FCH and DL-MAP are demodulated, pilot subcarriers in the Nth PUSC symbol have been used to estimate the channel of the Nth PUSC symbol.

    摘要翻译： 提供了一种信道估计装置和方法。 在信道估计装置中，信道估计器对所接收的符号进行信道估计并输出信道估计结果。 信道估计结果与在前置码相位补偿器中补偿的信道估计结果一起存储在估计缓冲器中。 前导码相位补偿器从估计缓冲器接收数据符号的导频子载波的信道估计结果和前导信道估计结果，获取相位旋转值，并以相位旋转值补偿前导信道估计结果。 当FCH和DL-MAP被解调时，第N PUSC符号中的导频子载波已被用于估计第N个PUSC符号的信道。