公开(公告)号：US07696556B2

公开(公告)日：2010-04-13

申请号：US11518724

申请日：2006-09-11

申请人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

发明人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L29/7887 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

摘要： High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.

摘要翻译： 提供了具有浮置漏极侧辅助栅极的高压MOS晶体管。 高压MOS晶体管包括设置在半导体衬底中的源极区域和漏极区域。 主栅极设置在漏区和源区之间的半导体衬底之上。 下侧漏极侧辅助栅极和上部漏极侧辅助栅极依次堆叠在主栅极和漏极区域之间的半导体衬底上。 下漏极侧辅助栅极与半导体基板，主栅电极和上漏极侧辅助栅极电绝缘。 还提供了制造高压MOS晶体管的方法。

公开(公告)号：US20070063257A1

公开(公告)日：2007-03-22

申请号：US11518724

申请日：2006-09-11

申请人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

发明人： Sung-Hoi Hur ,  Young-Min Park ,  Sang-Bin Song ,  Min-Cheol Park ,  Ji-Hwon Lee ,  Su-Youn Yi ,  Jang-Min Yoo

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L29/7887 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

摘要： High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.

摘要翻译： 提供了具有浮置漏极侧辅助栅极的高压MOS晶体管。 高压MOS晶体管包括设置在半导体衬底中的源极区域和漏极区域。 主栅极设置在漏区和源区之间的半导体衬底之上。 下侧漏极侧辅助栅极和上部漏极侧辅助栅极依次堆叠在主栅极和漏极区域之间的半导体衬底上。 下漏极侧辅助栅极与半导体基板，主栅电极和上漏极侧辅助栅极电绝缘。 还提供了制造高压MOS晶体管的方法。

公开(公告)号：US07391071B2

公开(公告)日：2008-06-24

申请号：US11233857

申请日：2005-09-23

申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

公开(公告)号：US20060063331A1

公开(公告)日：2006-03-23

申请号：US11233857

申请日：2005-09-23

申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

公开(公告)号：US20070048922A1

公开(公告)日：2007-03-01

申请号：US11509007

申请日：2006-08-24

申请人： Ji-Hwon Lee ,  Sung-Hoi Hur

发明人： Ji-Hwon Lee ,  Sung-Hoi Hur

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。 具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。 选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

公开(公告)号：US07608507B2

公开(公告)日：2009-10-27

申请号：US12216393

申请日：2008-07-03

申请人： Ji-Hwon Lee ,  Sung-Hoi Hur

发明人： Ji-Hwon Lee ,  Sung-Hoi Hur

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。 具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。 选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

公开(公告)号：US20080268595A1

公开(公告)日：2008-10-30

申请号：US12216393

申请日：2008-07-03

申请人： Ji-Hwon Lee ,  Sung-Hoi Hur

发明人： Ji-Hwon Lee ,  Sung-Hoi Hur

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。 具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。 选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

公开(公告)号：US07411239B2

公开(公告)日：2008-08-12

申请号：US11509007

申请日：2006-08-24

申请人： Ji-Hwon Lee ,  Sung-Hoi Hur

发明人： Ji-Hwon Lee ,  Sung-Hoi Hur

IPC分类号： H01L27/108

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。 具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。 选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

公开(公告)号：US20120264268A1

公开(公告)日：2012-10-18

申请号：US13441124

申请日：2012-04-06

申请人： Ji-Hwon Lee

发明人： Ji-Hwon Lee

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/02

CPC分类号： H01L27/11526 ,  H01L21/76224

摘要： Methods of forming nonvolatile memory devices include forming first and second floating gate electrodes of first and second nonvolatile memory cells, respectively, at side-by-side locations on a substrate. The substrate is selectively etched to define a trench therein extending between the first and second floating gate electrodes. The trench is at least partially filled with a first electrical insulation pattern. An inorganic polysilazane-type spin-on-glass (SOG) layer is conformally deposited on the first and second floating gate electrodes and on the first electrical insulation pattern and then partially removed.

摘要翻译： 形成非易失性存储器件的方法包括分别在衬底上的并排位置形成第一和第二非易失性存储单元的第一和第二浮置栅电极。 衬底被选择性地蚀刻以限定在第一和第二浮栅之间延伸的沟槽。 沟槽至少部分地填充有第一电绝缘图案。 无机聚硅氮烷型旋涂玻璃（SOG）层共形沉积在第一和第二浮栅上和第一电绝缘图案上，然后被部分去除。