公开(公告)号：US08144481B2

公开(公告)日：2012-03-27

申请号：US12632853

申请日：2009-12-08

申请人： Sung-Joo Park ,  Ki-Hyun Ko ,  Myung-Hee Sung

发明人： Sung-Joo Park ,  Ki-Hyun Ko ,  Myung-Hee Sung

IPC分类号： H01R9/00

CPC分类号： H05K1/0246 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10159

摘要： A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.

摘要翻译： 存储系统包括： 具有存储器总线的主板，具有用于传送来自安装在主板上的存储器控​​制器的信号的布线的布线;安装在主板上的第一和第二模块插槽，并将布线连接到分别插入第一和第二存储器模块的第一和第二存储器模块; 第二模块插座，其中第一存储器模块包括连接到布线的第一电极，并且第二存储器模块包括连接到布线的第二电极，以及设置在主板上并被布置为主要双绞线的第一和第二短截线电阻器， 在第一和第二电极之间形成T分支连接结构的分支短截线电阻器和连接到布线的分支节点。

公开(公告)号：US07646212B2

公开(公告)日：2010-01-12

申请号：US11668397

申请日：2007-01-29

申请人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

发明人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

IPC分类号： H03K19/003

CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C5/14

摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

摘要翻译： 存储器系统包括存储器控制器，传输总线，功率分配器，第一存储器芯片和第二存储器芯片。 传输总线从存储器控制器耦合到功率分配器的第一节点，用于传送信号。 功率分配器的第一节点通过第一线耦合到功率分配器的第二节点，并且第一节点也经由第二线路耦合到功率分配器的第三节点。 第一存储器芯片经由第一分支总线耦合到第二节点，并且第二存储器芯片经由第二分支总线耦合到第三节点。 因此，可以减少由于阻抗不匹配引起的反射波，以增强信号完整性。

公开(公告)号：US20070267701A1

公开(公告)日：2007-11-22

申请号：US11645528

申请日：2006-12-27

申请人： Myung-Hee Sung ,  Young-Man Ahn

发明人： Myung-Hee Sung ,  Young-Man Ahn

IPC分类号： H01L29/76

CPC分类号： H01L27/0266

摘要： A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of the semiconductor chip is applied to the second ESD diode. In a second mode, a body voltage substantially equal to the power source voltage of the semiconductor chip is applied to the body of the first ESD diode and a body voltage substantially equal to the ground voltage of the semiconductor chip is applied to the second ESD diode.

摘要翻译： 用于半导体芯片的多模式静电放电（ESD）电路包括第一和第二ESD二极管。 在第一模式中，将大于半导体芯片的电源电压的体电压施加到第一ESD二极管，并且将小于半导体芯片的接地电压的体电压施加到第二ESD二极管。 在第二模式中，将基本上等于半导体芯片的电源电压的体电压施加到第一ESD二极管的主体，并且将基本上等于半导体芯片的接地电压的体电压施加到第二ESD二极管 。

公开(公告)号：US07764475B2

公开(公告)日：2010-07-27

申请号：US11645528

申请日：2006-12-27

申请人： Myung-Hee Sung ,  Young-Man Ahn

发明人： Myung-Hee Sung ,  Young-Man Ahn

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of the semiconductor chip is applied to the second ESD diode. In a second mode, a body voltage substantially equal to the power source voltage of the semiconductor chip is applied to the body of the first ESD diode and a body voltage substantially equal to the ground voltage of the semiconductor chip is applied to the second ESD diode.

摘要翻译： 用于半导体芯片的多模式静电放电（ESD）电路包括第一和第二ESD二极管。 在第一模式中，将大于半导体芯片的电源电压的体电压施加到第一ESD二极管，并且将小于半导体芯片的接地电压的体电压施加到第二ESD二极管。 在第二模式中，将基本上等于半导体芯片的电源电压的体电压施加到第一ESD二极管的主体，并且将基本上等于半导体芯片的接地电压的体电压施加到第二ESD二极管 。

公开(公告)号：US20070194968A1

公开(公告)日：2007-08-23

申请号：US11668397

申请日：2007-01-29

申请人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

发明人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

IPC分类号： H03M1/78

CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C5/14

摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

摘要翻译： 存储器系统包括存储器控制器，传输总线，功率分配器，第一存储器芯片和第二存储器芯片。 传输总线从存储器控制器耦合到功率分配器的第一节点，用于传送信号。 功率分配器的第一节点通过第一线耦合到功率分配器的第二节点，并且第一节点也经由第二线路耦合到功率分配器的第三节点。 第一存储器芯片经由第一分支总线耦合到第二节点，并且第二存储器芯片经由第二分支总线耦合到第三节点。 因此，可以减少由于阻抗不匹配引起的反射波，以增强信号完整性。