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    Metal oxide semiconductor (MOS) transistors having three dimensional channels
    3.
    发明授权
    Metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
    具有三维通道的金属氧化物半导体（MOS）晶体管

    公开(公告)号：US07473963B2

    公开(公告)日：2009-01-06

    申请号：US11854734

    申请日：2007-09-13

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

    Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same
    5.
    发明申请
    Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 有权
    具有垂直取向栅电极的场效应晶体管及其制造方法

    公开(公告)号：US20050062109A1

    公开(公告)日：2005-03-24

    申请号：US10945246

    申请日：2004-09-20

    申请人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

    发明人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/80

    CPC分类号： H01L29/78696 ,  H01L29/42336 ,  H01L29/42384 ,  H01L29/66787 ,  H01L29/66825

    摘要： A field effect transistor on an active region of a semiconductor substrate includes a vertically protruding thin-body portion of the semiconductor substrate and a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate. The transistor further includes an insulating layer surrounding an upper portion of the vertically oriented gate electrode and a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode. Accordingly, a T-shaped gate electrode is defined having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.

    摘要翻译： 在半导体衬底的有源区域上的场效应晶体管包括半导体衬底的垂直突出的薄体部分和至少部分地在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直取向的栅电极。 晶体管还包括围绕垂直取向的栅电极的上部的绝缘层和绝缘层上的横向取向的栅电极，并连接到垂直取向的栅电极的顶部。 因此，T形栅电极被限定为具有在半导体衬底的顶表面上的横向部分，并且具有至少部分至少部分在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直部分。

    Metal Oxide Semiconductor (MOS) Transistors Having Three Dimensional Channels
    6.
    发明申请
    Metal Oxide Semiconductor (MOS) Transistors Having Three Dimensional Channels 有权
    具有三维通道的金属氧化物半导体（MOS）晶体管

    公开(公告)号：US20080001218A1

    公开(公告)日：2008-01-03

    申请号：US11854734

    申请日：2007-09-13

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

    Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels
    7.
    发明授权
    Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
    形成具有三维通道的金属氧化物半导体（MOS）晶体管的方法

    公开(公告)号：US07285466B2

    公开(公告)日：2007-10-23

    申请号：US10909471

    申请日：2004-08-02

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

    Field effect transistors including vertically oriented gate electrodes extending inside vertically protruding portions of a substrate
    8.
    发明授权
    Field effect transistors including vertically oriented gate electrodes extending inside vertically protruding portions of a substrate 有权
    场效应晶体管包括在衬底的垂直突出部分内延伸的垂直取向的栅电极

    公开(公告)号：US07129541B2

    公开(公告)日：2006-10-31

    申请号：US10945246

    申请日：2004-09-20

    申请人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

    发明人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L3/113 ,  H01L31/119

    CPC分类号： H01L29/78696 ,  H01L29/42336 ,  H01L29/42384 ,  H01L29/66787 ,  H01L29/66825

    摘要： A field effect transistor on an active region of a semiconductor substrate includes a vertically protruding thin-body portion of the semiconductor substrate and a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate. The transistor further includes an insulating layer surrounding an upper portion of the vertically oriented gate electrode and a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode. Accordingly, a T-shaped gate electrode is defined having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.

    摘要翻译： 在半导体衬底的有源区域上的场效应晶体管包括半导体衬底的垂直突出的薄体部分和至少部分地在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直取向的栅电极。 晶体管还包括围绕垂直取向的栅电极的上部的绝缘层和绝缘层上的横向取向的栅电极，并连接到垂直取向的栅电极的顶部。 因此，T形栅电极被限定为具有在半导体衬底的顶表面上的横向部分，并且具有至少部分至少部分在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直部分。

    Double gate MOS transistors
    10.
    发明授权
    Double gate MOS transistors 失效
    双栅MOS晶体管

    公开(公告)号：US06940129B2

    公开(公告)日：2005-09-06

    申请号：US10715664

    申请日：2003-11-18

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654

    摘要： A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.

    摘要翻译： 双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。 至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。 半导体柱支撑晶体管有源区，使得晶体管有源区与衬底有源区间隔开。 至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。 底栅电极与衬底有源区，晶体管有源区和半导体柱绝缘。 至少一个顶栅电极跨越晶体管有源区，并且具有与底栅电极的侧壁接触的至少一个端。 顶栅电极与底栅电极重叠并与晶体管有源区绝缘。 还提供制造这种晶体管的方法。