公开(公告)号：US06759873B2

公开(公告)日：2004-07-06

申请号：US10153158

申请日：2002-05-21

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: H03K190185

CPC classification number: H03K19/0016

Abstract: A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.

Abstract translation: 公开了一种反向偏置逻辑电路，用于在电路操作期间限制备用漏电流损耗。 该电路包括具有一个或多个逻辑晶体管的逻辑功能电路，其接收输入并执行逻辑功能操作以产生输出。 电源晶体管连接到逻辑功能电路并接收在主动模式和待机模式之间改变一个或多个逻辑晶体管的节点电压的控制信号。 在待机模式期间，电源晶体管引起一个或多个逻辑晶体管中的至少一个逻辑晶体管的反向偏置，从而防止电源晶体管和一个或多个逻辑晶体管之间的漏电流流动。

公开(公告)号：US06977528B2

公开(公告)日：2005-12-20

申请号：US10325594

申请日：2002-12-20

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: H03K3/012 ,  H03K19/00 ,  H03K19/096

CPC classification number: H03K3/012 ,  H03K19/0016 ,  H03K19/0963

Abstract: Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

Abstract translation: 描述了方法和电路，用于当时钟信号不会在逻辑电路内产生期望的状态变化时，例如在输入，中间节点处，通过阻止时钟信号转换到逻辑电路来减少数字逻辑电路内的功耗， 输出或组合。 作为示例，如果要接收时钟信号转换，如果给定的一组逻辑输入不会导致状态的输出改变，则输入时钟被阻塞。 作为进一步的示例，如果输入信号与输出信号匹配，则输入时钟在数据触发器中被阻塞，使得接收到时钟转换将不会在锁存输出中产生期望的状态变化。 本发明可以用于创建较低功率的组合和/或顺序逻辑电路级，所述低功率组合和/或顺序的逻辑电路级经历栅极电容的不经济的充电和放电。

公开(公告)号：US06900690B2

公开(公告)日：2005-05-31

申请号：US10729726

申请日：2003-12-05

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: H03K3/012 ,  H03K19/00 ,  G05F1/10

CPC classification number: H03K3/012 ,  H03K19/0016

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

公开(公告)号：US07190209B2

公开(公告)日：2007-03-13

申请号：US11119283

申请日：2005-04-28

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: G05F1/10

CPC classification number: H03K3/012 ,  H03K19/0016

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract translation: 提供了一种集成电路，其包括具有第一PMOS晶体管和第一NMOS晶体管的多状态电路。 在活动模式中，多状态电路可操作以在其中第一PMOS晶体管导通并且第一NMOS晶体管截止的第一状态和第一PMOS晶体管截止的第二状态之间切换， 第一个NMOS晶体管导通。 电源NMOS晶体管具有连接到电源电压端子的漏极，并且源极连接到第一PMOS晶体管的源极。 电源PMOS晶体管具有连接到有效接地端子的漏极，并且源极连接到第一NMOS晶体管的源极。

公开(公告)号：US06946901B2

公开(公告)日：2005-09-20

申请号：US10155490

申请日：2002-05-22

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: H03K3/012 ,  H03K19/00 ,  G05F1/10

CPC classification number: H03K3/012 ,  H03K19/0016

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

公开(公告)号：US20050201144A1

公开(公告)日：2005-09-15

申请号：US11118938

申请日：2005-04-28

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: H03K3/012 ,  H03K3/356 ,  H03K3/3565 ,  H03K19/00 ,  G11C11/00

CPC classification number: H03K3/3565 ,  G11C11/412 ,  G11C2207/2227 ,  H03K3/012 ,  H03K3/356156 ,  H03K19/0016

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate coupled to a first access control node; and a second low threshold voltage access transistor including a first S/D coupled to the second data node and to the gate of the first PMOS transistor and to the gate of the first NMOS transistor and including a second S/D coupled to a second data access node and including a gate coupled to a second access control node.

公开(公告)号：US20070205470A1

公开(公告)日：2007-09-06

申请号：US11601120

申请日：2006-11-17

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: H01L29/76

CPC classification number: H03K3/3565 ,  G11C11/412 ,  G11C2207/2227 ,  H03K3/012 ,  H03K3/356156 ,  H03K19/0016

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate coupled to a first access control node; and a second low threshold voltage access transistor including a first S/D coupled to the second data node and to the gate of the first PMOS transistor and to the gate of the first NMOS transistor and including a second S/D coupled to a second data access node and including a gate coupled to a second access control node.

Abstract translation: 提供一种集成电路，包括一个锁存电路，该锁存电路包括：第一反相器，包括第一高阈值电压PMOS晶体管和第一高阈值电压NMOS晶体管，第一数据节点包括第一PMOS的互连源/漏极（S / D） NMOS晶体管; 包括第二高阈值电压PMOS晶体管和第二高阈值电压NMOS晶体管的第二反相器，其中第二数据节点包括第二PMOS和NMOS晶体管的互连源/漏极（S / D）; 其中所述第一PMOS和所述第一NMOS晶体管的栅极耦合到所述第二数据节点; 其中所述第二PMOS晶体管和所述第二NMOS晶体管的栅极耦合到所述第一数据节点; 第一低阈值电压存取晶体管，包括耦合到第一数据节点和第二PMOS晶体管的栅极和第二NMOS晶体管的栅极的第一S / D并且包括耦合到第一数据存取的第二S / D 并且包括耦合到第一接入控制节点的门; 以及第二低阈值电压存取晶体管，其包括耦合到所述第二数据节点和所述第一PMOS晶体管的栅极和所述第一NMOS晶体管的栅极的第一S / D并且包括耦合到第二数据的第二S / D 接入节点并且包括耦合到第二接入控制节点的门。

公开(公告)号：US20050190633A1

公开(公告)日：2005-09-01

申请号：US11119283

申请日：2005-04-29

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: H03K3/012 ,  H03K19/00 ,  G11C8/00

CPC classification number: H03K3/012 ,  H03K19/0016

Abstract: An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Abstract translation: 提供了一种集成电路，其包括具有第一PMOS晶体管和第一NMOS晶体管的多状态电路。 在活动模式中，多状态电路可操作以在其中第一PMOS晶体管导通并且第一NMOS晶体管截止的第一状态和第一PMOS晶体管截止的第二状态之间切换， 第一个NMOS晶体管导通。 电源NMOS晶体管具有连接到电源电压端子的漏极，并且源极连接到第一PMOS晶体管的源极。 电源PMOS晶体管具有连接到有效接地端子的漏极，并且源极连接到第一NMOS晶体管的源极。

公开(公告)号：US07466191B2

公开(公告)日：2008-12-16

申请号：US11286197

申请日：2005-11-22

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: G11C5/14

CPC classification number: H03K3/3565 ,  G11C11/412 ,  G11C2207/2227 ,  H03K3/012 ,  H03K3/356156 ,  H03K19/0016

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.

Abstract translation: 提供一种集成电路，包括第一NMOS晶体管; 第一PMOS晶体管; 第二NMOS晶体管; 第二PMOS晶体管; 耦合到所述第一NMOS晶体管的第一源极/漏极的第一偏置电压节点; 耦合到所述第二PMOS的第一源极/漏极的第二偏置电压节点; 耦合到所述第一PMOS晶体管的栅极的第三偏置电压节点; 耦合到所述第二NMOS晶体管的栅极的第四偏置电压节点; 将所述第一NMOS晶体管的第二源极/漏极耦合到所述第一PMOS晶体管的第一源极/漏极的上拉节点; 将所述第二PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第一源极/漏极的下拉节点; 输入节点; 将所述第一PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第二源极/漏极的存储节点; 输出节点; 一个输入开关，其被耦合以可控地传送来自输入节点的输入数据值到第一NMOS晶体管的栅极和第二PMOS晶体管的栅极; 以及输出开关，其耦合以可控制地将存储的数据值从存储节点传送到输出节点。

公开(公告)号：US20060083052A1

公开(公告)日：2006-04-20

申请号：US11286197

申请日：2005-11-22

Applicant: Sung-Mo Kang ,  Seung-Moon Yoo

Inventor： Sung-Mo Kang ,  Seung-Moon Yoo

IPC: G11C11/00

CPC classification number: H03K3/3565 ,  G11C11/412 ,  G11C2207/2227 ,  H03K3/012 ,  H03K3/356156 ,  H03K19/0016

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.

Abstract translation: 提供一种集成电路，包括第一NMOS晶体管; 第一PMOS晶体管; 第二NMOS晶体管; 第二PMOS晶体管; 耦合到所述第一NMOS晶体管的第一源极/漏极的第一偏置电压节点; 耦合到所述第二PMOS的第一源极/漏极的第二偏置电压节点; 耦合到所述第一PMOS晶体管的栅极的第三偏置电压节点; 耦合到所述第二NMOS晶体管的栅极的第四偏置电压节点; 将所述第一NMOS晶体管的第二源极/漏极耦合到所述第一PMOS晶体管的第一源极/漏极的上拉节点; 将所述第二PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第一源极/漏极的下拉节点; 输入节点; 将所述第一PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第二源极/漏极的存储节点; 输出节点; 一个输入开关，其被耦合以可控地传送来自输入节点的输入数据值到第一NMOS晶体管的栅极和第二PMOS晶体管的栅极; 以及输出开关，其耦合以可控制地将存储的数据值从存储节点传送到输出节点。