公开(公告)号：US06738417B1

公开(公告)日：2004-05-18

申请号：US09393849

申请日：1999-09-09

申请人： Sungjoon Kim ,  Deog-Kyoon Jeong ,  David D. Lee

发明人： Sungjoon Kim ,  Deog-Kyoon Jeong ,  David D. Lee

IPC分类号： H04B138

CPC分类号： H04L5/14 ,  G06F3/14 ,  G09G1/16 ,  G09G2370/045

摘要： A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally without sending the additional backward clock. This invention also discloses a scheme to tolerate jitters from the clock source. With this approach, this new interface can make a digital display an I/O concentrator.

摘要翻译： 公开了一种在数字显示器和计算机之间传输双向数据流的新方案。 这种双向数据传输可以使多个I / O设备连接到显示器。 现有的数字显示接口通常是从计算到显示的单向的。 由于现有的时钟方案的性质，从显示侧到计算机的反向数据传输需要一个反向时钟。 本发明公开了一种双向发送数据的方案，而不发送额外的反向时钟。 本发明还公开了一种允许来自时钟源的抖动的方案。 通过这种方式，这个新界面可以使数字显示器成为一个I / O集中器。

公开(公告)号：US6151334A

公开(公告)日：2000-11-21

申请号：US187559

申请日：1998-11-04

申请人： Sungjoon Kim ,  David D. Lee ,  Deog-Kyoon Jeong

发明人： Sungjoon Kim ,  David D. Lee ,  Deog-Kyoon Jeong

IPC分类号： G09G5/00 ,  G06F13/40 ,  H03M9/00 ,  H04J3/00 ,  H04J3/04 ,  H04J3/06 ,  H04L5/00 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L25/08 ,  H04L25/49 ,  H04N7/083 ,  H04N7/52 ,  H04N21/2368 ,  H04N21/434 ,  H04J3/16

CPC分类号： H04N7/52 ,  G06F13/4018 ,  H03M9/00 ,  H04J3/0605 ,  H04L25/085 ,  H04L25/4915 ,  H04L7/0337 ,  H04N21/23602 ,  H04N21/4342 ,  H04N7/083 ,  H04L2007/045 ,  H04L7/0008

摘要： A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data streams and then merges the encoded data into a serial stream that is output across a serial line to the removing unit. The removing unit receives a serial stream of data, decodes the serial stream, and then separates the decoded serial stream into separate streams thereby reconstructing the streams input to the embedding unit. The encoding and transmission by the embedding unit and the receipt and decoding by the removing unit are completely transparent, the signals output by the removing unit are identical in timing and data content to the signals input to the embedding unit. The present invention also includes a method for transmitting a plurality of data streams over a signal line, and a method for generating a plurality of data streams from a serial sequence.

摘要翻译： 用于通过串行链路发送多个数据信号的系统和方法包括嵌入单元和通过串行线耦合的去除单元。 嵌入单元优选地接收多个数据流，对数据流进行编码，然后将经编码的数据合并成串行流，该串行流通过串行线输出到移除单元。 去除单元接收串行数据流，解码串行流，然后将解码的串行流分离成单独的流，从而重建输入到嵌入单元的流。 嵌入单元的编码和发送以及由去除单元的接收和解码完全透明，由去除单元输出的信号在定时和数据内容上与输入到嵌入单元的信号相同。 本发明还包括通过信号线发送多个数据流的方法，以及用于从串行序列生成多个数据流的方法。

公开(公告)号：US5835498A

公开(公告)日：1998-11-10

申请号：US664136

申请日：1996-06-14

申请人： Sungjoon Kim ,  David D. Lee ,  Deog-Kyoon Jeong

发明人： Sungjoon Kim ,  David D. Lee ,  Deog-Kyoon Jeong

IPC分类号： G09G5/00 ,  G06F13/40 ,  H03M9/00 ,  H04J3/00 ,  H04J3/04 ,  H04J3/06 ,  H04L5/00 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L25/08 ,  H04L25/49 ,  H04N7/083 ,  H04N7/52 ,  H04N21/2368 ,  H04N21/434 ,  H04J3/16

CPC分类号： H04N7/52 ,  G06F13/4018 ,  H03M9/00 ,  H04J3/0605 ,  H04L25/085 ,  H04L25/4915 ,  H04L7/0337 ,  H04N21/23602 ,  H04N21/4342 ,  H04N7/083 ,  H04L2007/045 ,  H04L7/0008

摘要： A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data streams and then merges the encoded data into a serial stream that is output across a serial line to the removing unit. The removing unit receives a serial stream of data, decodes the serial stream, and then separates the decoded serial stream into separate streams thereby reconstructing the streams input to the embedding unit. The encoding and transmission by the embedding unit and the receipt and decoding by the removing unit are completely transparent, the signals output by the removing unit are identical in timing and data content to the signals input to the embedding unit. The present invention also includes a method for transmitting a plurality of data streams over a signal line, and a method for generating a plurality of data streams from a serial sequence.

公开(公告)号：US07113507B2

公开(公告)日：2006-09-26

申请号：US10053461

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J3/12 ,  H04L12/56

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

公开(公告)号：US07257129B2

公开(公告)日：2007-08-14

申请号：US10045297

申请日：2001-11-07

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J15/00 ,  G06F13/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US07154905B2

公开(公告)日：2006-12-26

申请号：US10035911

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J15/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US07039121B2

公开(公告)日：2006-05-02

申请号：US10045393

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong

IPC分类号： H04L25/34 ,  H04L25/49

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

公开(公告)号：US06976201B2

公开(公告)日：2005-12-13

申请号：US10036794

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J99/00 ,  G06F12/00 ,  G11C8/00 ,  H03M5/00 ,  H03M13/00 ,  H04J1/16 ,  H04J3/06 ,  H04J3/12 ,  H04J3/16 ,  H04J3/22 ,  H04L1/00 ,  H04L7/00 ,  H04L12/00 ,  H04L12/28 ,  H04L12/56 ,  H04L29/06

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture can provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture can also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，非对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如下面更详细地描述的 。 Storage Link架构还可以指定编码技术来优化转换并确保DC平衡。

公开(公告)号：US6157360A

公开(公告)日：2000-12-05

申请号：US815486

申请日：1997-03-11

申请人： Deog-Kyoon Jeong ,  Gyudong Kim ,  Ho Young Song ,  David D. Lee

发明人： Deog-Kyoon Jeong ,  Gyudong Kim ,  Ho Young Song ,  David D. Lee

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2310/027 ,  G09G3/3696

摘要： Described is a system and method for driving columns of an active matrix display using a resistor-string digital-to-analog converter (DAC). The description includes an auto-stop buffer circuit that drives an analog data voltage in two steps--the first step being active buffering by a "dead-zone amplifier" before the output reaches a certain level and the second step being acting as a passive conduit after the output reaches the certain level. The dead-zone amplifier inherently turns itself off when the analog voltage reaches the certain level. Also described are various column driver architectures in which buffers are placed in various ways in a column driver in between the resistor-string DAC and the column decoders in order to minimize the number of required buffers.

摘要翻译： 描述了一种使用电阻串数模转换器（DAC）驱动有源矩阵显示器列的系统和方法。 该描述包括以两步驱动模拟数据电压的自动停止缓冲电路 - 第一步是在输出达到一定水平之前由“死区放大器”进行主动缓冲，第二步用作无源导管 输出达到一定水平后。 当模拟电压达到一定水平时，死区放大器本身就会自动关闭。 还描述了各种列驱动器架构，其中缓冲器以各种方式放置在电阻器串DAC和列解码器之间的列驱动器中，以便使所需缓冲器的数量最小化。

公开(公告)号：US6100868A

公开(公告)日：2000-08-08

申请号：US937262

申请日：1997-09-15

申请人： Deog-Kyoon Jeong ,  David D. Lee

发明人： Deog-Kyoon Jeong ,  David D. Lee

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0297

摘要： To reduce the layout area required by LCD column drivers without suffering a significant decrease in performance, a PMOS-based circuit selects a voltage from an upper set of analog display voltages and a NMOS-based circuit selects a voltage from a lower set of analog display voltages. This reduces the layout area by up to roughly a factor of two compared with conventional column drivers which are CMOS-based. Moreover, in a typical dot inversion scheme, where two adjacent columns select voltages from alternating voltage sets, two adjacent columns can share the same PMOS-based and NMOS-based circuits by using multiplexers controlled by a polarity signal to route the digital display data into the sets of switches. This reduces the layout area by up to roughly an additional factor of two.

摘要翻译： 为了减少LCD列驱动器所需的布局面积而不会显着降低性能，基于PMOS的电路从上一组模拟显示电压中选择电压，并且基于NMOS的电路从下一组模拟显示器中选择电压 电压。 与基于CMOS的常规列驱动器相比，这将减少布局面积达2倍左右。 此外，在典型的点反转方案中，其中两个相邻列选择来自交变电压组的电压，两个相邻列可以通过使用由极性信号控制的多路复用器来共享相同的基于PMOS和NMOS的电路，以将数字显示数据路由到 开关组。 这样可以将布局面积减少大约两倍。