Verification of Ethernet hardware based on checksum correction with cyclic redundancy check

    公开(公告)号:US11979232B2

    公开(公告)日:2024-05-07

    申请号:US17943712

    申请日:2022-09-13

    Applicant: Synopsys, Inc.

    CPC classification number: H04L1/0061 H04L1/24 H04L43/106

    Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.

    Debug methodology for a USB sub-system using unique identifier (UID) approach

    公开(公告)号:US11809363B1

    公开(公告)日:2023-11-07

    申请号:US17462753

    申请日:2021-08-31

    Applicant: Synopsys, Inc.

    Abstract: A method for debugging an electronic subsystem is disclosed. The method includes converting a first message in a first protocol format received at a first functional logical block of a plurality of functional logical blocks of an electronic subsystem into a second message in a second protocol format at the first functional logical block, wherein the second message includes a unique identifier (UID), and generating a first trace file corresponding to the first functional logical block, wherein the first trace file includes the UID. The method includes forwarding the second message from the first functional logical block to a second functional logical block. The method includes generating a second trace file corresponding to the second functional logical block, wherein the second trace file includes the UID, and performing an analysis on the first and the second functional logical blocks.

    VERIFICATION OF ETHERNET HARDWARE BASED ON CHECKSUM CORRECTION WITH CYCLIC REDUNDANCY CHECK

    公开(公告)号:US20230086197A1

    公开(公告)日:2023-03-23

    申请号:US17943712

    申请日:2022-09-13

    Applicant: Synopsys, Inc.

    Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.

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