公开(公告)号：US07298020B2

公开(公告)日：2007-11-20

申请号：US10797081

申请日：2004-03-11

申请人： Syuji Asano ,  Yoshiaki Nakayama ,  Koji Eguchi

发明人： Syuji Asano ,  Yoshiaki Nakayama ,  Koji Eguchi

IPC分类号： H01L29/00

CPC分类号： H01L28/24 ,  H01L21/8221 ,  H01L27/0688

摘要： A wire (12) is formed on an insulating film (10) on a semiconductor substrate (1). The wire (12) is covered by silicon nitride film (14), inorganic SOG film (20) and TEOS film (21). A thin film resistance element (30) of chromium silicon (CrSi) is formed on the upper surface of the TEOS film (21). The acute angle (taper angle) at which a line connecting the local maximum and minimum points of a step on the upper surface of the TEOS film (21) beneath the area where the thin film resistance element (30) is formed intersects to the surface of the substrate (1) is set to 10° or less.

摘要翻译： 在半导体衬底（1）上的绝缘膜（10）上形成导线（12）。 线（12）由氮化硅膜（14），无机SOG膜（20）和TEOS膜（21）覆盖。 在TEOS膜（21）的上表面上形成有铬硅（CrSi）的薄膜电阻元件（30）。 连接薄膜电阻元件（30）形成区域下方的TEOS薄膜（21）的上表面上的台阶的局部最大值和最小点的线的锐角（锥角）与表面 的基板（1）设定为10°以下。

公开(公告)号：US5200807A

公开(公告)日：1993-04-06

申请号：US520482

申请日：1990-05-08

申请人： Koji Eguchi

发明人： Koji Eguchi

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L2924/0002

摘要： A wiring connection structure for a semiconductor integrated circuit device interconnects a plurality of wiring layers isolated by an insulating layer, via a through hole defined in the insulating layer. The wiring connection structure comprises a semiconductor substrate, a first insulating layer, a first wiring layer, a second insulating layer and a second wiring layer. The first insulating layer is formed on a main surface of the semiconductor substrate. The first wiring layer is formed on the first insulating layer. The second insulating layer is formed on the first wiring layer. The through hole is formed in the second insulating layer so as to extend to a surface of the first wiring layer. The second wiring layer is formed on the second insulating layer and connected to the first wiring layer via the through hole. The through hole is a single through hole formed in a region where the second wiring layer overlaps with the first wiring layer. The through hole has a cross section comprising a figure formed by indenting peripheries of a single rectangular figure. This cross section has a longer perimeter than the single rectangular figure. Alternatively, the cross section comprises a figure formed by interconnecting band portions extending along the second wiring layer. A reduction is achieved in components of resistance over an entire through hole forming region. Concentration of current density on side walls of the through hole is also mitigated.

摘要翻译： 用于半导体集成电路器件的布线连接结构通过绝缘层中限定的通孔将由绝缘层隔离的多个布线层互连。 布线连接结构包括半导体衬底，第一绝缘层，第一布线层，第二绝缘层和第二布线层。 第一绝缘层形成在半导体衬底的主表面上。 第一布线层形成在第一绝缘层上。 第二绝缘层形成在第一布线层上。 通孔形成在第二绝缘层中，以便延伸到第一布线层的表面。 第二布线层形成在第二绝缘层上，并且经由通孔与第一布线层连接。 通孔是形成在第二布线层与第一布线层重叠的区域中的单个通孔。 通孔具有包括通过压制单个矩形图形的外围形成的图形的横截面。 该横截面具有比单个矩形图形更长的周长。 或者，横截面包括通过互连沿着第二布线层延伸的带部分形成的图形。 在整个通孔形成区域中的电阻分量中实现了减小。 通孔侧壁电流密度的集中也得到了缓解。

公开(公告)号：US06705450B2

公开(公告)日：2004-03-16

申请号：US09765428

申请日：2001-01-22

申请人： Koji Eguchi

发明人： Koji Eguchi

IPC分类号： B65G1500

CPC分类号： H01L21/67724

摘要： In a clean room having a plurality of floors of different levels, an escalator is disposed between the plurality of floors for transporting an article between the floors. A self-propelled vehicle is used for transporting an article between floors. The self-propelled vehicle and the article are loaded on a step of the escalator. The vehicle and the article are held on the step from above the article by means of a holding section. The holding section assists loading of the vehicle onto the escalator through the article in the vicinity of an entrance gate of the escalator and assists unloading of the vehicle from the escalator in the vicinity of an exit gate.

摘要翻译： 在具有不同层次的多个楼层的洁净室中，自动扶梯设置在多个楼层之间，用于在楼层之间运送物品。 自走式车辆用于在楼层之间运送物品。 自走车辆和物品装载在自动扶梯的台阶上。 车辆和物品通过保持部分保持在物品上方的台阶上。 控股部分通过自动扶梯入口附近的物品协助将车辆装载到自动扶梯上，并协助在出口附近的自动扶梯上卸下车辆。

公开(公告)号：US4849854A

公开(公告)日：1989-07-18

申请号：US119893

申请日：1987-11-12

申请人： Koji Eguchi

发明人： Koji Eguchi

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L28/40 ,  H01L29/945

摘要： Two or three trenches are formed in a silicon substrate, and a conductive layer is formed in the silicon substrate facing the trenches. An oxide film for insulation is formed on a surface of the conductive layer facing the trenches. The trenches are filled with polysilicon, and the conductive layer and the polysilicon constitute a capacitor through the oxide film. Since this capacitor has two or three trenches, an effective area sufficiently large for increasing a capacitance value of the capacitor can be obtained without increasing the plane area of the device. The conductive layer and the polysilicon are connected to aluminum interconnection layers through a silicide layer, so as to be connected to other integrated circuits.

摘要翻译： 在硅衬底中形成两个或三个沟槽，并且在硅衬底中形成面向沟槽的导电层。 在面向沟槽的导电层的表面上形成用于绝缘的氧化物膜。 沟槽填充有多晶硅，导电层和多晶硅通过氧化膜构成电容器。 由于该电容器具有两个或三个沟槽，所以可以在不增加器件的平面面积的情况下获得足够大的用于增加电容器的电容值的有效面积。 导电层和多晶硅通过硅化物层连接到铝互连层，以便连接到其他集成电路。

公开(公告)号：US06595428B2

公开(公告)日：2003-07-22

申请号：US09730601

申请日：2000-12-07

申请人： Koji Eguchi ,  Hiroshi Mochizuki ,  Tamio Matsumura

发明人： Koji Eguchi ,  Hiroshi Mochizuki ,  Tamio Matsumura

IPC分类号： G06K1906

CPC分类号： G06Q10/06 ,  G05B19/41865 ,  G05B2219/31388 ,  G05B2219/31432 ,  G05B2219/36115 ,  G05B2219/36371 ,  Y02P90/20

摘要： A process control method allowing an operator to readily confirm an order of operation processes includes steps of: reading magnetic data of a control card when the control card is inserted; transmitting completion data based on a lot number identified from read magnetic data to a host computer; receiving update data by the host computer; writing next process data in the received data as a visually recognizable image on the control card; and writing the next process data as a visually recognizable image based on process data identified by the read magnetic data when a predetermined time period passes without receiving update data.

公开(公告)号：US5471084A

公开(公告)日：1995-11-28

申请号：US94142

申请日：1993-07-30

申请人： Yasutoshi Suzuki ,  Kenichi Ao ,  Hirofumi Uenoyama ,  Hiroki Noguchi ,  Koji Eguchi ,  Ichiro Ito ,  Yoshimi Yoshino

发明人： Yasutoshi Suzuki ,  Kenichi Ao ,  Hirofumi Uenoyama ,  Hiroki Noguchi ,  Koji Eguchi ,  Ichiro Ito ,  Yoshimi Yoshino

IPC分类号： H01L43/08 ,  H01L27/22

CPC分类号： H01L43/08

摘要： This invention relates to a magnetoresistive element used for a magnetic sensor, etc. A ferromagnetic magnetoresistive element thin film is formed so as to be electrically connected to and so as to overlap the upper end portion of an aluminum wiring metal on a substrate. Through using a vacuum heat treatment with a temperature between 350.degree. and 450.degree. C., a Ni--Al-based alloy is formed at the overlapping portion. Therefore, even when a surface protection film of silicon nitride is subsequently formed by plasma CVD on the substrate, the alloy prevents the nitriding of the upper end portion of the aluminum wiring metal. Accordingly, the surface can be protected from moisture by the silicon nitride film without increasing the contact resistance between the magnetoresistive element thin film and the wiring metal. Instead of the Ni--Al-based alloy, other conductive metals such as TiW, TiN, Ti, Zr, or the like may be used. Also, the surface protection film may be a multi-layered film having a first film containing no nitrogen, such as a silicon oxide film, and a second film of silicon nitride film formed on the first film.

摘要翻译： PCT No.PCT / JP92 / 01581 Sec。 371日期：1993年7月30日 102（e）日期1993年7月30日PCT提交1992年12月3日PCT公布。 公开号WO93 / 11569 日本特许公报1993年6月10日。本发明涉及用于磁传感器等的磁阻元件。铁磁磁阻元件薄膜形成为与铝布线的上端部电连接并与其重叠 金属在基板上。 通过使用350〜450℃的真空热处理，在重叠部分形成Ni-Al系合金。 因此，即使在基板上随后通过等离子体CVD形成氮化硅的表面保护膜，合金也能防止铝布线金属的上端部的氮化。 因此，可以防止表面被氮化硅膜防止湿气，而不增加磁阻元件薄膜和布线金属之间的接触电阻。 可以使用TiW，TiN，Ti，Zr等其他导电性金属代替Ni-Al系合金。 此外，表面保护膜也可以是具有不含氮的第一膜的多层膜，例如氧化硅膜，以及形成在第一膜上的第二氮化硅膜。

公开(公告)号：US07016749B2

公开(公告)日：2006-03-21

申请号：US10267569

申请日：2002-10-10

申请人： Seigo Kuzumaki ,  Yoshio Shirai ,  Takatoshi Negishi ,  Kazuhiro Miyauchi ,  Masato Kato ,  Katsuhiko Kato ,  Yasushi Okamoto ,  Shouichi Okumura ,  Mikio Sato ,  Yoshiki Konishi ,  Morio Oba ,  Koji Sato ,  Junichi Harada ,  Shigeharu Ueyama ,  Koji Eguchi ,  Goro Takahashi

发明人： Seigo Kuzumaki ,  Yoshio Shirai ,  Takatoshi Negishi ,  Kazuhiro Miyauchi ,  Masato Kato ,  Katsuhiko Kato ,  Yasushi Okamoto ,  Shouichi Okumura ,  Mikio Sato ,  Yoshiki Konishi ,  Morio Oba ,  Koji Sato ,  Junichi Harada ,  Shigeharu Ueyama ,  Koji Eguchi ,  Goro Takahashi

IPC分类号： G06F19/00

CPC分类号： G06F17/5095

摘要： A product design CAD data reconstruction unit 50 reconstructs product design CAD data used for product evaluation regarding an initial design so as to fulfill restrictive conditions obtained from the product evaluation based on a product structure for the initial design. The reconstructed product design CAD data is stored in a product design CAD data database 90. Upon reception of a corrected design obtained by correcting the initial design, the product design CAD data for the initial design is read from the product design CAAD data database 90, and the product design CAD data is corrected along a design surface of the corrected design.

摘要翻译： 产品设计CAD数据重建单元50重建用于关于初始设计的产品评估的产品设计CAD数据，以便实现基于初始设计的产品结构从产品评估获得的限制条件。 重建产品设计CAD数据存储在产品设计CAD数据数据库90中。 在接收到通过校正初始设计获得的校正设计后，从产品设计CAAD数据数据库90读取用于初始设计的产品设计CAD数据，并且沿着校正设计的设计表面校正产品设计CAD数据。

公开(公告)号：US06194907B1

公开(公告)日：2001-02-27

申请号：US09326604

申请日：1999-06-07

申请人： Tsuyoshi Kanao ,  Koji Eguchi ,  Toru Yamaguchi

发明人： Tsuyoshi Kanao ,  Koji Eguchi ,  Toru Yamaguchi

IPC分类号： G01R3102

CPC分类号： G01R31/2886

摘要： A prober can make an appropriate evaluation in a microcurrent region. A wafer (9) is disposed on a chuck (8) in a casing (1). In the upper surface of the chuck (8), an electrode (8a) is formed which is connected to a power supply (11) via a wire (10). In the casing (1), a cylindrical electromagnetic shielding box (7) is disposed with the upper surface open. The upper surface of the casing (1) and the side surfaces and bottom surface of the electromagnetic shielding box (7) form a closed space (30) for surrounding the chuck (8) and the wafer (9). Also, a loader (6) for driving the chuck (8) and the electromagnetic shielding box (7) is disposed in the casing (1). On the upper surface of the casing (1), a tester head (3) is disposed with a probe card (4) disposed therein. Since part of the upper surface of the casing (1) is open, probe needles (5) of the probe card (4) protrude into the casing (1) through the opening.

摘要翻译： 探测者可以在微流过程中进行适当的评估。 晶片（9）设置在壳体（1）中的卡盘（8）上。 在卡盘（8）的上表面形成电极（8a），通过导线（10）与电源（11）连接。 在壳体（1）中，在上表面打开的状态下设置圆柱形电磁屏蔽箱（7）。 壳体（1）的上表面和电磁屏蔽箱（7）的侧表面和底表面形成用于围绕卡盘（8）和晶片（9）的封闭空间（30）。 此外，用于驱动卡盘（8）和电磁屏蔽箱（7）的装载机（6）设置在壳体（1）中。 在壳体（1）的上表面上，设置有设置有探针卡（4）的测试头（3）。 由于壳体（1）的上表面的一部分开放，所以探针卡（4）的探针（5）通过开口突出到壳体（1）中。

公开(公告)号：US4859622A

公开(公告)日：1989-08-22

申请号：US227333

申请日：1988-08-02

申请人： Koji Eguchi

发明人： Koji Eguchi

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L28/40 ,  H01L29/945

摘要： Two or three trenches are formed in a silicon substrate, and a conductive layer is formed in the silicon substrate facing the trenches. An oxide film for insulation is formed on a surface of the conductive layer facing the trenches. The trenches are filled with polysilicon, and the conductive layer and the polysilicon constitute a capacitor through the oxide film. Since this capacitor has two or three trenches, an effective area sufficiently large for increasing a capacitance value of the capacitor can be obtained without increasing the plane area of the device. The conductive layer and the polysilicon are connected to aluminum interconnection layers through a silicide layer, so as to be connected to other integrated circuits.

摘要翻译： 在硅衬底中形成两个或三个沟槽，并且在硅衬底中形成面向沟槽的导电层。 在面向沟槽的导电层的表面上形成用于绝缘的氧化物膜。 沟槽填充有多晶硅，导电层和多晶硅通过氧化膜构成电容器。 由于该电容器具有两个或三个沟槽，所以可以在不增加器件的平面面积的情况下获得足够大的用于增加电容器的电容值的有效面积。 导电层和多晶硅通过硅化物层连接到铝互连层，以便连接到其他集成电路。

公开(公告)号：US06748704B2

公开(公告)日：2004-06-15

申请号：US09784024

申请日：2001-02-16

申请人： Koji Eguchi ,  Shintaro Matsuda ,  Satoru Souda ,  Akiko Sakai

发明人： Koji Eguchi ,  Shintaro Matsuda ,  Satoru Souda ,  Akiko Sakai

IPC分类号： E04H900

CPC分类号： E04H5/02 ,  E04B2001/0084 ,  E04H1/005 ,  Y10S52/10

摘要： A factory layout includes a plurality of substantially triangle units provided in radial directions. The triangle units are combined so as to form a polygonal shape including a triangle shape as a whole. The empty regions with an air-conditioning facility are provided at a part of the central portion of the polygonal shape.

摘要翻译： 工厂布置包括沿径向设置的多个基本三角形的单元。 组合三角形单元以形成整体上包括三角形的多边形形状。 具有空调设备的空区域设置在多边形形状的中心部分的一部分。