公开(公告)号：US20100027316A1

公开(公告)日：2010-02-04

申请号：US12465125

申请日：2009-05-13

申请人： TAE-EUNG YOON ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： TAE-EUNG YOON ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/025

摘要： A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

摘要翻译： 具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。 提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。 提供耦合在多个位线和多个可变电阻器之间的多个选择晶体管。

公开(公告)号：US07894265B2

公开(公告)日：2011-02-22

申请号：US12081679

申请日：2008-04-18

申请人： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

发明人： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

IPC分类号： G11C5/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/0483 ,  H01L27/11521 ,  H01L27/11568

摘要： The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.

摘要翻译： 非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。 编程存储器件的目标单元的方法包括激活连接到目标单元的主串和子串的选择晶体管。

公开(公告)号：US20090122613A1

公开(公告)日：2009-05-14

申请号：US12149213

申请日：2008-04-29

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

IPC分类号： G11C16/06 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C2213/71

摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.

摘要翻译： 非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。 多个NAND串可以在多个半导体层上。 多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。 公共位线可以在存储器单元的第一端处共同连接到每个NAND串。 公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。 多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

公开(公告)号：US07796432B2

公开(公告)日：2010-09-14

申请号：US12149213

申请日：2008-04-29

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2213/71

摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.

摘要翻译： 非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。 多个NAND串可以在多个半导体层上。 多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。 公共位线可以在存储器单元的第一端处共同连接到每个NAND串。 公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。 多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

公开(公告)号：US07986545B2

公开(公告)日：2011-07-26

申请号：US12465125

申请日：2009-05-13

申请人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/025

摘要： A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

摘要翻译： 具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。 提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。 耦合在多个位线和多个可变电阻之间的多个选择晶体管被设置。

公开(公告)号：US20090091975A1

公开(公告)日：2009-04-09

申请号：US12081679

申请日：2008-04-18

申请人： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

发明人： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  H01L27/11521 ,  H01L27/11568

摘要： Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor.

摘要翻译： 提供了一种非易失性存储器件及其操作方法。 非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。

公开(公告)号：US20090285027A1

公开(公告)日：2009-11-19

申请号：US12318651

申请日：2009-01-05

申请人： Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

发明人： Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

摘要翻译： 提供了包括与多个位线和多个字线耦合的多个存储晶体管的非易失性存储器件以及操作非易失性存储器件的方法。 从多个位线确定用于编程的选择位线和用于防止编程的未选位线。 对从多个字线中选择的至少一个禁止字线施加抑制电压。 至少一个禁止字线包括最靠近字符串选择线定位的字线。 将编程电压施加到从多个字线中选择的选定字线。 数据被编程到与所选择的字线和所选择的位线耦合的存储晶体管中，同时防止数据被编程到与未选位线耦合的存储晶体管中。

公开(公告)号：US07885115B2

公开(公告)日：2011-02-08

申请号：US12318651

申请日：2009-01-05

申请人： Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

发明人： Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

摘要翻译： 提供了包括与多个位线和多个字线耦合的多个存储晶体管的非易失性存储器件以及操作非易失性存储器件的方法。 从多个位线确定用于编程的选择位线和用于防止编程的未选位线。 对从多个字线中选择的至少一个禁止字线施加抑制电压。 至少一个禁止字线包括最靠近字符串选择线定位的字线。 将编程电压施加到从多个字线中选择的选定字线。 数据被编程到与所选择的字线和所选择的位线耦合的存储晶体管中，同时防止数据被编程到与未选位线耦合的存储晶体管中。

公开(公告)号：US07813180B2

公开(公告)日：2010-10-12

申请号：US12005376

申请日：2007-12-27

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C7/00

CPC分类号： H01L29/7881 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.

摘要翻译： 示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。 示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。 第一电荷存储层可以在半导体衬底和第一控制栅电极之间。 源区域可以在第一控制栅电极的一侧的半导体衬底中限定。 第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。 第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。 位线可以连接到第一漏区。

公开(公告)号：US20080175061A1

公开(公告)日：2008-07-24

申请号：US12005376

申请日：2007-12-27

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C16/06 ,  H01L29/788

CPC分类号： H01L29/7881 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.

摘要翻译： 示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。 示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。 第一电荷存储层可以在半导体衬底和第一控制栅电极之间。 源区域可以在第一控制栅电极的一侧的半导体衬底中限定。 第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。 第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。 位线可以连接到第一漏区。