公开(公告)号：US20120252155A1

公开(公告)日：2012-10-04

申请号：US13428792

申请日：2012-03-23

Applicant: Sang-Jun CHOI ,  June-Mo Koo ,  Duck-Hyung Lee ,  Jong-Cheol Shin ,  Yu-Jin Ahn ,  Eun-Kyung Park ,  Sun-E Park

Inventor： Sang-Jun CHOI ,  June-Mo Koo ,  Duck-Hyung Lee ,  Jong-Cheol Shin ,  Yu-Jin Ahn ,  Eun-Kyung Park ,  Sun-E Park

IPC: H01L31/18 ,  H01L21/04

CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L21/268 ,  H01L27/14632 ,  H01L27/14683 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

Abstract: In a method of doping impurities, an amorphous layer is formed on a substrate. Impurities are implanted through a top surface of the amorphous layer to form a first doping region at an upper portion of the substrate. The first doping region and the amorphous layer are transformed into a second doping region and a recrystallized layer, respectively, by a laser annealing process. The recrystallized layer is removed.

Abstract translation: 在掺杂杂质的方法中，在基板上形成非晶层。 通过非晶层的顶表面注入杂质以在衬底的上部形成第一掺杂区。 第一掺杂区和非晶层分别通过激光退火工艺转变成第二掺杂区和再结晶层。 去除重结晶层。

公开(公告)号：US20120119180A1

公开(公告)日：2012-05-17

申请号：US13355878

申请日：2012-01-23

Applicant: June-mo KOO ,  Suk-pil KIM ,  Tae-Eung YOON

Inventor： June-mo KOO ,  Suk-pil KIM ,  Tae-Eung YOON

IPC: H01L47/00

CPC classification number: H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

Abstract: Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

Abstract translation: 提供了可以以堆叠结构进行扩展并因此可以高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。 所述非易失性存储器件包括：至少一个第一电极，至少一个第二电极，与所述至少一个第一电极交叉，至少一个数据存储层插入在所述至少一个第一电极和所述第二电极之间的区域中 所述至少一个第一电极与所述至少一个第二电极交叉，并且所述至少一个金属硅化物层插入在所述至少一个第一电极和所述至少一个第二电极之间，所述至少一个第一电极在所述至少一个第一电极与 至少一个第二电极。

公开(公告)号：US20100117054A1

公开(公告)日：2010-05-13

申请号：US12557580

申请日：2009-09-11

Applicant: Deok-kee Kim ,  June-mo Koo ,  Ju-chul Park ,  Kyoung-won Na ,  Dong-seok Suh ,  Bum-seok Seo ,  Yoon-dong Park

Inventor： Deok-kee Kim ,  June-mo Koo ,  Ju-chul Park ,  Kyoung-won Na ,  Dong-seok Suh ,  Bum-seok Seo ,  Yoon-dong Park

IPC: H01L47/00

CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/249 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1666

Abstract: Provided is a non-volatile memory device including at least one horizontal electrode, at least one vertical electrode, at least one data storage layer and at least one reaction prevention layer. The least one vertical electrode crosses the at least one horizontal electrode. The at least one data storage layer is located in regions in which the at least one vertical electrode crosses the at least one horizontal electrode, and stores data by varying its electrical resistance. The at least one reaction prevention layer is located in the regions in which the at least one vertical electrode crosses the at least one horizontal electrode.

Abstract translation: 提供了包括至少一个水平电极，至少一个垂直电极，至少一个数据存储层和至少一个反应防止层的非易失性存储器件。 至少一个垂直电极与至少一个水平电极交叉。 所述至少一个数据存储层位于所述至少一个垂直电极与所述至少一个水平电极交叉的区域中，并且通过改变其电阻来存储数据。 所述至少一个反应防止层位于所述至少一个垂直电极与所述至少一个水平电极交叉的区域中。

公开(公告)号：US20100065899A1

公开(公告)日：2010-03-18

申请号：US12544631

申请日：2009-08-20

Applicant: Suk-pil Kim ,  Yoon-dong Park ,  Jae-young Choi ,  June-mo Koo ,  Byung-hee Hong

Inventor： Suk-pil Kim ,  Yoon-dong Park ,  Jae-young Choi ,  June-mo Koo ,  Byung-hee Hong

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/66833 ,  B82Y10/00 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device may include first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode may be provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes may be configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.

Abstract translation: 半导体器件可以包括第一和第二辅助栅极电极以及与第一和第二辅助栅电极交叉的半导体层。 主栅电极可以设置在半导体层上，使得半导体层位于主栅极和第一和第二辅助栅电极之间。 此外，第一和第二辅助栅电极可以被配置为在半导体层中诱发相应的第一和第二场效应型源极/漏极区。 还讨论了相关方法。

公开(公告)号：US20090091975A1

公开(公告)日：2009-04-09

申请号：US12081679

申请日：2008-04-18

Applicant: Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

Inventor： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

IPC: G11C16/06

CPC classification number: G11C16/0483 ,  H01L27/11521 ,  H01L27/11568

Abstract: Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor.

Abstract translation: 提供了一种非易失性存储器件及其操作方法。 非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。

公开(公告)号：US20080157182A1

公开(公告)日：2008-07-03

申请号：US11980632

申请日：2007-10-31

Applicant: Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-Woong Hyun ,  Sung-jae Byun

Inventor： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-Woong Hyun ,  Sung-jae Byun

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

Abstract translation: 示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。 半导体器件包括半导体衬底，半导体柱和接触插塞。 半导体衬底包括至少一对使用（或功能）作为活性区的翅片。 半导体柱可以插入翅片的部分之间以连接散热片。 接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

公开(公告)号：US20080157176A1

公开(公告)日：2008-07-03

申请号：US11902511

申请日：2007-09-21

Applicant: Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Sung-jae Byun

Inventor： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Sung-jae Byun

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66803

Abstract: A nonvolatile memory device having lower bit line contact resistance and a method of fabricating the same is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type may include first and second fins. A common bit line electrode may connect one end of the first fin to one end of the second fin. A plurality of control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode may be positioned between the common bit line electrode and the plurality of control gate electrodes. The first string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode may be positioned between the first string selection gate electrode and the plurality of control gate electrodes. The second string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. The first fin under the first string selection gate electrode and the second fin under the second string selection gate electrode may have a second conductivity type opposite to the first conductivity type.

Abstract translation: 提供一种具有较低位线接触电阻的非易失性存储器件及其制造方法。 在非易失性存储器件中，第一导电类型的半导体衬底可以包括第一和第二鳍片。 公共位线电极可将第一鳍片的一端连接到第二鳍片的一端。 多个控制栅极电极可以覆盖第一和第二鳍片并且跨越第一和第二鳍片中的每一个的顶表面膨胀。 第一串选择栅极可以位于公共位线电极和多个控制栅电极之间。 第一串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。 第二串选择栅电极可以位于第一串选择栅电极和多个控制栅电极之间。 第二串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。 第一串选择栅电极下的第一鳍和第二串选择栅电极下的第二鳍可以具有与第一导电类型相反的第二导电类型。

公开(公告)号：US20080135916A1

公开(公告)日：2008-06-12

申请号：US11987008

申请日：2007-11-26

Applicant: Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim

Inventor： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/7885 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

Abstract: Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.

Abstract translation: 提供了非易失性存储器件的示例性实施例及其制造方法。 非易失性存储器件可以包括布置在半导体衬底上的控制栅电极，介于半导体衬底和控制栅电极之间的栅极绝缘层，介于栅极绝缘层和控制栅电极之间的存储节点层， 插入在所述存储节点层和所述控制栅电极之间的阻挡绝缘层，沿着所述控制栅电极的第一侧的第一掺杂剂掺杂区域和沿着所述控制栅电极的第二侧的第二掺杂剂掺杂区域。 第一掺杂剂掺杂区域可以与第二掺杂剂掺杂区域交替。 换句话说，每个第二掺杂剂掺杂区域可以被布置在与第一掺杂剂掺杂区域中的一个相邻的控制栅电极的第二侧上的区域中。

公开(公告)号：US20080123390A1

公开(公告)日：2008-05-29

申请号：US11882694

申请日：2007-08-03

Applicant: Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

Inventor： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC: G11C11/00 ,  H01L21/16

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  H01L27/24

Abstract: A non-volatile memory device and a method of fabricating the same are provided. In the non-volatile memory device, at least one first semiconductor layer of a first conductivity type may be formed spaced apart from each other on a portion of a substrate. A plurality of first resistance variation storage layers may contact first sidewalls of each of the at least one first semiconductor layer. A plurality of second semiconductor layers of a second conductivity type, opposite to the first conductivity type, may be interposed between the first sidewalls of each of the at least one first semiconductor layer and the plurality of first resistance variation storage layers. A plurality of bit line electrodes may be connected to each of the plurality of first resistance variation storage layers.

Abstract translation: 提供了一种非易失性存储器件及其制造方法。 在非易失性存储器件中，第一导电类型的至少一个第一半导体层可以在衬底的一部分上彼此间隔开形成。 多个第一电阻变化存储层可以接触至少一个第一半导体层中的每一个的第一侧壁。 与第一导电类型相反的第二导电类型的多个第二半导体层可以插入在至少一个第一半导体层和多个第一电阻变化存储层中的每一个的第一侧壁之间。 多个位线电极可以连接到多个第一电阻变化存储层中的每一个。

公开(公告)号：US20070224347A1

公开(公告)日：2007-09-27

申请号：US11525026

申请日：2006-09-22

Applicant: Jin Sung Lee ,  Tae Gyu Kim ,  June Mo Koo ,  Chang Hoon Jung

Inventor： Jin Sung Lee ,  Tae Gyu Kim ,  June Mo Koo ,  Chang Hoon Jung

IPC: B05C11/02 ,  B05B3/00 ,  B05D7/00 ,  B05D3/12

CPC classification number: H01L21/6715 ,  B05D1/005 ,  B05D1/02 ,  G03F7/162

Abstract: A liquid coating apparatus and method for spraying a liquid on a wafer. The liquid coating apparatus may include a nozzle unit spraying the liquid on the wafer and moving relative to the wafer and a laminar flow forming unit forming a forced air flow around the nozzle unit. Though a wake may be formed around the nozzle unit by a movement of the nozzle unit, the laminar forming unit may reduce and/or minimize an influence of the wake.

Abstract translation: 一种用于将液体喷射在晶片上的液体涂覆装置和方法。 液体涂布装置可以包括将液体喷射在晶片上并相对于晶片移动的喷嘴单元和形成在喷嘴单元周围的强制空气流的层流形成单元。 虽然可以通过喷嘴单元的运动在喷嘴单元周围形成尾流，但是层流形成单元可以减少和/或最小化尾流的影响。