公开(公告)号：US20190341445A1

公开(公告)日：2019-11-07

申请号：US16512315

申请日：2019-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chiun LIN ,  Po-Nien CHEN ,  Chen Hua TSAI ,  Chih-Yung LIN

IPC分类号： H01L49/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02 ,  H01L23/522 ,  H01L21/3205 ,  H01L27/092

摘要： A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US20200328270A1

公开(公告)日：2020-10-15

申请号：US16914528

申请日：2020-06-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chiun LIN ,  Po-Nien CHEN ,  Chen Hua TSAI ,  Chih-Yung LIN

IPC分类号： H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L27/06 ,  H01L23/522 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/3205

摘要： A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US20180190754A1

公开(公告)日：2018-07-05

申请号：US15593479

申请日：2017-05-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chiun LIN ,  Po-Nien CHEN ,  Chen Hua TSAI ,  Chih-Yung LIN

IPC分类号： H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L27/06

CPC分类号： H01L28/24 ,  H01L21/32051 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US20170125412A1

公开(公告)日：2017-05-04

申请号：US15089114

申请日：2016-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Wei SOONG ,  Chih-Pin TSAO ,  Hou-Yu CHEN ,  Chen Hua TSAI

IPC分类号： H01L27/088 ,  H01L21/3115 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823493

摘要： In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.

公开(公告)号：US20170125413A1

公开(公告)日：2017-05-04

申请号：US15096004

申请日：2016-04-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Sheng WU ,  Chen Hua TSAI ,  Hou-Yu CHEN ,  Chia-Wei SOONG ,  Chih-Pin TSAO

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/167

CPC分类号： H01L27/0886 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/167

摘要： In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.